Electrostatic writing system utilizing tapped delay lines

Claim 1

AN ELECTROSTATIC WRITING TRANSDUCER COMPRISING A FIRST DELAY LINE HAVING A PLURALITY OF TAPS ALONG THE LENGTH THEREOF, A PLURALITY OF BUS BARS A DIFFERENT ONE OF WHICH IS CONNECTED TO EACH OF SAID TAPS, A PLURALITY OF GROUPS OF WRITING STYLI, A DIFFERENT ONE OF THE WRITING STYLI IN EACH GROUP BEING CONNECTED TO A DIFFERENT ONE OF SAID BUS BARS, SAID GROUPS OF STYLI EXTENDING FROM SAID BUS BARS TO A COMMON PLANE, A CONDUCTIVE BAR FOR EACH GROUP OF WRITING STYLI, EACH SAID CONDUCTIVE BAR BEING POSITIONED OPPOSITE A GROUP OF WRITING STYLI AT SAID COMMON PLANE, A SECOND DELAY LINE HAVING A PLURALITY OF TAPS THEREALONG, THE NUMBER OF SAID SECOND DELAY-LINE TAPS CORRESPONDING TO THE NUMBER OF CONDUCTIVE BARS, MEANS FOR CONNECTING EACH CONDUCTIVE BAR TO A DIFFERENT ONE OF SAID TAPS, AND MEANS FOR APPLYING SIGNALS TO SAID FIRST AND SECOND DELAY LINES TO ENABLE ELECTROSTATIC DISCHARGES TO OCCUR BETWEEN SAID STYLI AND EACH CONDUCTIVE BARS IN A PREORDERED SEQUENCE INCLUDING A FIRST SOURCE OF PULSES HAVING ONE POLARITY, MEANS FOR APPLYING PULSES FROM SAID FIRST SOURCE TO ONE END OF SAID FIRST DELAY LINE, A SECOND SOURCE OF PULSES HAVING A POLARITY OPPOSITE TO SAID ONE POLARITY, MEANS FOR APPLYING PULSES FROM SAID SECOND SOURCE TO ONE END OF SAID SECOND DELAY LINE, A SOURCE OF INTELLIGENCE SIGNALS, AND MEANS FOR APPLYING SAID INTELLIGENCE SIGNALS TO BOTH ENDS OF SAID SECOND DELAY LINE TO CAUSE AN ELECTROSTATIC DISCHARGE BETWEEN A STYLUS AND CONDUCTIVE BAR ONLY IN THE PRESENCE OF A FIRST AND SECOND PULSE AND AN INTELLIGENCE SIGNAL.