Parallel data skew correction system

Claim 1

IN A SYSTEM FOR REPRODUCING MULTI-CHANNEL PARALLEL BIT INFORMATION SIGNALS FORM SELF-CLOCKING SIGNALS RECEIVED IN SKEWED ARRAY, THE COMBINATION SIGNALS FROM SKEWED PARSEPARATE CLOCK AND INFORMATION SIGNALS FROM SKEWED PARALLEL BIT SELF-CLOCKING SIGNALS, A PLURALITY OF BIT STORAGE DEVICES IN NUMBER EQUAL TO THE NUMBER OF BITS IN ONE OF SAID PARALLEL SIGNALS TIMES A PREDETERMINED INTEGER, AN "AND" GATE FOR EACH OF SAID STORAGE DEVICES COUPLED TO SAID INFORMATION SIGNAL DERIVING MEANS, AT LEAST ONE SHIFT REGISTER FOR EACH OF SAID BITS COMPRISING A SINGLE PARALLEL SIGNAL COUPLED TO SAID "AND" GATES, CIRCUITS COUPLING SAID CLOCK SIGNAL DERIVING MEANS WITH SAID SHIFT REGISTER TO CIRCULATE A SIGNAL TO ACTUATE SAID "AND" GATES FOR DIRECTING INFORMATION SIGNAL BITS FROM SAID INFORMATION SIGNAL DERIVING MEANS TO SAID STORAGE DEVICES, DELAY MEANS FOR DELAYING ONE OF SAID CLOCK SIGNALS, ADDITIONAL "AND" GATES CONNECTED TO SAID STORAGE DEVICES, AN ADDITIONAL SHIFT REGISTER COUPLED TO SAID DELAY MEANS FOR PROVIDING A STEPPING SIGNAL, COUPLINGS BETWEEN SAID ADDITIONAL SHIFT RGISTER AND SAID ADDITIONAL "AND" GATES TO DIRECT DELAYED STEPPING SIGNALS TO THE LAST SAID GATES FOR FEEDING STORED BITS OUT OF SAID STORAGE MEANS, "OR" GATES AT LEAST EQUAL IN NUMBER TO THE NUMBER OF BITS PER PARALLEL SIGNAL CONNECTED TO SAID ADDITIONAL "AND" GATES, FURTHER "AND" GATES AT LEAST EQUAL IN NUMBER TO THE NUMBER OF BITS PER PARALLEL SIGNAL CONNECTED ONE EACH TO SAID "OR" GATES, ADDITIONAL DELAY MEANS COUPLED TO THE FIRST SAID DELAY MEANS FOR FURTHER DELAYING SAID CLOCK SIGNALS, AND COUPLING BETWEEN SAID ADDITIONAL DELAY MEANS AND SAID FURTHER "AND" GATES FOR STEPPING OUT DESKEWED PARALLEL BIT SIGNALS.