Patent US626700A successfully refreshed from Google Patents.
US3192402A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Delay network
Assignee: AT&T Inc
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Filing: 1961-03-09
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Granted: 1965-06-29
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Expires: 1981-03-09
Abstract
No abstract record available.
Inventors
- 👤 Irwin W Sandberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:17
CPC Classifications
H; H03; H03H; H03H19/00; H03H19/002; H03H11/00; H03H11/02; H03H11/26
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
176 words
A DELAY NETWORK HAVING AN INPUT TERMINAL, AN OUTPUT TERMINAL, AND A GROUND TERMINAL AND COMPRISING A TRANSISTOR HAVING A BASE, A COLLECTOR, AND AN EMITTER, A PATH FROM THE BASE TO THE INPUT TERMINAL, A PATH FROM THE COLLECTOR TO THE OUTPUT TERMINAL, A RESISTOR OF VALUE R4 CONNECTED BETWEEN THE BASE AND THE COLLECTOR, AND TWO IMPEDANCE PATHS CONNECTED IN PARALLEL BETWEEN THE EMITTER AND THE GROUND TERMINAL, ONE OF THE PARALLEL PATHS INCLUDING A BIASING RESISTOR AND THE OTHER PARALLEL PATH INCLUDING N CAPACITORS, EACH OF VALUE C, AND MEANS FOR CONNECTING THE CAPACITORS INTO CIRCUIT SEQUENTIALLY AND REPETITIVELY IN A PERIOD OF TIME T WITH A DWELL TIME D FOR EACH CAPACITOR, THE NETWORK BEING ADAPTED TO OPERATE BETWEEN A RESISTIVE INPUT IMPEDANCE R1 AND A RESISTIVE OUTPUT IMPEDANCE R2 AND C, D, N, R1, R2, AND R4 BEING SO CHOSEN WITH RESPECT TO T AND THE AMPLIFICATION FACTOR OF THE TRANSISTOR THAT THE NETWORK HAS A SUBSTANTIALLY CONSTANT AMPLITUDE CHARACTERISTIC AND A SUBSTANTIALLY CONSTANT DELAY T AT ALL FREQUENCIES BELOW N/2T.
Claim 2
Dependent Claim
176 words
A DELAY NETWORK HAVING AN INPUT TERMINAL, AN OUTPUT TERMINAL, AND A GROUND TERMINAL AND COMPRISING A TRANSISTOR HAVING A BASE, A COLLECTOR, AND AN EMITTER, A PATH FROM THE BASE TO THE INPUT TERMINAL, A PATH FROM THE COLLECTOR TO THE OUTPUT TERMINAL, A RESISTOR OF VALUE R4 CONNECTED BETWEEN THE BASE AND THE COLLECTOR, AND TWO IMPEDANCE PATHS CONNECTED IN PARALLEL BETWEEN THE EMITTER AND THE GROUND TERMINAL, ONE OF THE PARALLEL PATHS INCLUDING A BIASING RESISTOR AND THE OTHER PARALLEL PATH INCLUDING N CAPACITORS, EACH OF VALUE C, AND MEANS FOR CONNECTING THE CAPACITORS INTO CIRCUIT SEQUENTIALLY AND REPETITIVELY IN A PERIOD OF TIME T WITH A DWELL TIME D FOR EACH CAPACITOR, THE NETWORK BEING ADAPTED TO OPERATE BETWEEN A RESISTIVE INPUT IMPEDANCE R1 AND A RESISTIVE OUTPUT IMPEDANCE R2 AND C, D, N, R1, R2, AND R4 BEING SO CHOSEN WITH RESPECT TO T AND THE AMPLIFICATION FACTOR OF THE TRANSISTOR THAT THE NETWORK HAS A SUBSTANTIALLY CONSTANT AMPLITUDE CHARACTERISTIC AND A SUBSTANTIALLY CONSTANT DELAY T AT ALL FREQUENCIES BELOW N/2T.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-06-28 | 1968-12-28 | 1969-06-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-06-28 | 1972-12-28 | 1973-06-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-06-28 | 1976-12-28 | 1977-06-29 | $7700.00 | Window Closed / Lapsed |