US3188491A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transmission or blocking gate
Assignee: Individual
•
Filing: 1962-09-25
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Granted: 1965-06-08
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Expires: 1982-09-25
Abstract
No abstract record available.
Inventors
- 👤 Bahn Raymond W La
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:07
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/72
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
154 words
IN A GATING CIRCUIT THE COMBINATION COMPRISING: (A) A FIRST TRANSISTOR HAVING A BASE, COLLECTOR AND AN EMITTER, (B) A SCHMIDT TRIGGER GENERATOR FOR GENERATING POSITIVE AND NEGATIVE CONTROL PULSES, (C) THE BASE OF SAID FIRST TRANSISTOR BEING COUPLED TO THE OUTPUT OF SAID SCHMIDT TRIGGER GENERATOR, (D) SECOND AND THIRD TRANSISTORS EACH HAVING A BASE, COLLECTOR AND EMITTER, (E) RESISTOR CIRCUIT MEANS CONNECTING THE EMITTERS OF SAID SECOND AND THIRD TRANSISTORS, (F) FIRST RECTIFYING MEANS CONNECTED BETWEEN THE COLLECTOR OF SAID FIRST TRANSISTOR AND THE EMITTER OF SAID SECOND TRANSISTOR, (G) SECOND RECTIFYING MEANS BEING OPPOSITELY POLARIZED TO THAT OF SAID FIRST RECTIFYING MEANS CONNECTED BETWEEN THE EMITTER OF SAID FIRST TRANSISTOR AND THE EMITTER OF SAID THIRD TRANSISTOR, (H) CIRCUIT MEANS COUPLING AN INPUT SIGNAL TO BE GATED TO THE BASED OF SAID SECOND AND THIRD TRNSISTORS AND (I) OUTPUT CIRCUIT MEANS COUPLED TO THE COLLECTORS OF SAID SECOND AND THIRD TRANSISTORS.
Claim 2
Dependent Claim
154 words
IN A GATING CIRCUIT THE COMBINATION COMPRISING: (A) A FIRST TRANSISTOR HAVING A BASE, COLLECTOR AND AN EMITTER, (B) A SCHMIDT TRIGGER GENERATOR FOR GENERATING POSITIVE AND NEGATIVE CONTROL PULSES, (C) THE BASE OF SAID FIRST TRANSISTOR BEING COUPLED TO THE OUTPUT OF SAID SCHMIDT TRIGGER GENERATOR, (D) SECOND AND THIRD TRANSISTORS EACH HAVING A BASE, COLLECTOR AND EMITTER, (E) RESISTOR CIRCUIT MEANS CONNECTING THE EMITTERS OF SAID SECOND AND THIRD TRANSISTORS, (F) FIRST RECTIFYING MEANS CONNECTED BETWEEN THE COLLECTOR OF SAID FIRST TRANSISTOR AND THE EMITTER OF SAID SECOND TRANSISTOR, (G) SECOND RECTIFYING MEANS BEING OPPOSITELY POLARIZED TO THAT OF SAID FIRST RECTIFYING MEANS CONNECTED BETWEEN THE EMITTER OF SAID FIRST TRANSISTOR AND THE EMITTER OF SAID THIRD TRANSISTOR, (H) CIRCUIT MEANS COUPLING AN INPUT SIGNAL TO BE GATED TO THE BASED OF SAID SECOND AND THIRD TRNSISTORS AND (I) OUTPUT CIRCUIT MEANS COUPLED TO THE COLLECTORS OF SAID SECOND AND THIRD TRANSISTORS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1968-06-07 | 1968-12-07 | 1969-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1972-06-07 | 1972-12-07 | 1973-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1976-06-07 | 1976-12-07 | 1977-06-08 | $7700.00 | Window Closed / Lapsed |