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US3183131A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor diffusion method

Assignee: Motorola Solutions Inc
•
Filing: 1961-08-23
•
Granted: 1965-05-11
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Expires: 1981-08-23
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Abstract

No abstract record available.

Inventors

  • 👤 Tomuaie R Huffman

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 12:11
CPC Classifications
C; C30; C30B; C30B31/00; C30B31/06; C30B31/16; C30B31/165; C30B31/14; H; H10; H10P; H10P95/00; Y; Y10; Y10S; Y10S252/00; Y10S252/95; Y10S252/951

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 162 words
A METHOD OF DIFFUSING IMPURITIES INTO SEMICONDUCTOR WAFERS BY PRE-DEPOSITION AND REDISTRIBUTION AND CHARACTERIZED BY UNIFORM DIFFUSION CONDITIONS AND RESULTS ACROSS EACH WAFER AND FROM WAFER TO WAFER, SAID METHOD INCUDING THE STEPS OF COATING AN IMPURITY OXIDE MATERIAL ON A FLAT SUFACE OF A BCKING MEMBER, HEATING SAID BACKING MEMBER TO GLAZE SAID COATING THEREON, PLACING A PLURALITY OF SEMICONDUCTOR WAFERS IN A CLOSURE STRUCTURE WHICH INCLUDES SAID BACKING MEMBER SUCH THAT SAID WAFERS ALL LIE FLAT IN THE SAME PLANE SEPARATED THE SAME DISTANCE FROM AND PARALLEL TO THE IMPURITY MATERIAL ON SAID BACKING MEMBER, PLACING SAID CLOSURE STRUCTURE IN A HEATED REGION OF A DIFFUSION SYSTEM MAINTAINED AT A TEMPERATURE TO CAUSE VAPORIZATION OF IMPURITY MATERIAL FROM SAID BACKING MEMBER AND DIFFUSION OF IMPURITY MATERIAL INTO SAID WAFERS UNTIL A MAXIMUM CONCENTRATION OF THE IMPURITY FOR SAID TEMPERATURE EXISTS IN A SURFACE REGION OF EACH WAFER, AND SUBSEQUENTLY HEATING SAID WAFERS TO REDISTRIBUTE THE IMPURITIES INSAID WAFERS BY DIFFUSION.
Claim 2
Independent Claim 162 words
A METHOD OF DIFFUSING IMPURITIES INTO SEMICONDUCTOR WAFERS BY PRE-DEPOSITION AND REDISTRIBUTION AND CHARACTERIZED BY UNIFORM DIFFUSION CONDITIONS AND RESULTS ACROSS EACH WAFER AND FROM WAFER TO WAFER, SAID METHOD INCUDING THE STEPS OF COATING AN IMPURITY OXIDE MATERIAL ON A FLAT SUFACE OF A BCKING MEMBER, HEATING SAID BACKING MEMBER TO GLAZE SAID COATING THEREON, PLACING A PLURALITY OF SEMICONDUCTOR WAFERS IN A CLOSURE STRUCTURE WHICH INCLUDES SAID BACKING MEMBER SUCH THAT SAID WAFERS ALL LIE FLAT IN THE SAME PLANE SEPARATED THE SAME DISTANCE FROM AND PARALLEL TO THE IMPURITY MATERIAL ON SAID BACKING MEMBER, PLACING SAID CLOSURE STRUCTURE IN A HEATED REGION OF A DIFFUSION SYSTEM MAINTAINED AT A TEMPERATURE TO CAUSE VAPORIZATION OF IMPURITY MATERIAL FROM SAID BACKING MEMBER AND DIFFUSION OF IMPURITY MATERIAL INTO SAID WAFERS UNTIL A MAXIMUM CONCENTRATION OF THE IMPURITY FOR SAID TEMPERATURE EXISTS IN A SURFACE REGION OF EACH WAFER, AND SUBSEQUENTLY HEATING SAID WAFERS TO REDISTRIBUTE THE IMPURITIES INSAID WAFERS BY DIFFUSION.

References Cited (Backward Citations)

US2845894A Cited
US2804405A Cited
US2870049A Cited
US2975080A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1968-05-10 1968-11-09 1969-05-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1972-05-10 1972-11-09 1973-05-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1976-05-10 1976-11-09 1977-05-11 $7700.00 Window Closed / Lapsed

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