Self-synchronizing delay line data recirculation loop

Claim 1

IN A DELAY LINE DATA STORAGE SYSTEM, AN INFORMATION LOOP, A CLOCK LOOP, A DELAY LINE COMMON TO AN INFORMATION LOOP AND SAID CLOCK LOOP FOR STORING A PULSE TRAIN HAVING FIRST INTELLIGENCE BEARING PORTIONS INCLUDING FIRST AND SECOND TYPES OF SIGNALS AND SECOND TIMING PORTIONS INTERTWINED WITH SAID FIRST INTELLIGENCE BEARING PORTIONS, A WRITE-IN CIRCUIT COMMON TO BOTH OF SAID LOOPS, MEANS WITHIN SAID INFORMATION LOOP FOR FORWARDING SIGNALS REPRESENTATIVE OF SAID FIRST PORTIONS EMERGING FROM SAID DELAY LINE TO SAID WRITE-IN CIRCUIT, MEANS WITHIN SAID CLOCK LOOP FOR FORWARDING SIGNALS REPRESENTATIVE OF SAID SECOND PORTIONS EMERGING FROM SAID DELAY LINE TO SAID WRITE-IN CIRCUIT SUBSTANTIALLY COINCIDENT WITH THE FORWARDING OF SAID SIGNALS REPRESENTATIVE OF SAID FIRST PORTIONS TO SAID WRITE-IN CIRCUIT BY SAID MEANS FOR FORWARDING WITHIN SAID INFORMATION LOOP, SAID WRITE-IN CIRCUIT FURTHER INCLUDING MEANS FOR CAUSING FIRST TYPES OF SIGNALS TO BE INSERTED INTO SAID DELAY LINE IN RESPONSE TO THE APPLICATION OF SAID SECOND PORTIONS TO SAID WRITE-IN CIRCUIT VIA SAID CLOCK LOOP WHERE SIGNALS REPRESENTATIVE OF FIRST TYPES OF SIGNALS ARE SIMULTANEOUSLY APPLIED TO SAID WRITE-IN CIRCUIT VIA SAID INFORMATION LOOP AND FOR CAUSING SECOND TYPES OF SIGNALS TO BE INTRODUCED INTO SAID DELAY LINE IN RESPONSE TO THE APPLICATION OF SAID SECOND PORTIONS TO SAID WRITE-IN CIRCUIT VIA SAID CLOCK LOOP WHERE SIGNALS REPRESENTATIVE OF SECOND TYPES OF SIGNALS ARE SIMULTANEOUSLY APPLIED TO SAID WRITE-IN CIRCUIT VIA SAID INFORMATION LOOP.