US3160805A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Battery charger
Assignee: Individual
•
Filing: 1960-12-28
•
Granted: 1964-12-08
•
Expires: 1980-12-28
Abstract
No abstract record available.
Inventors
- 👤 Jr Wilmer M Lawson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:25
CPC Classifications
H; H02; H02J; H02J7/00; H02J7/90; H02J7/96; Y; Y10; Y10S; Y10S320/00; Y10S320/18; Y10S320/19; Y10S320/27
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
206 words
A BATTERY CHARGER COMPRISING; (A) A PAIR OF INPUT TERMINALS FOR CONNECTION TO AN ALTERNATING CURRENT SOURCE; (B) A PAIR OF OUTPUT CHARGING TERMINALS FOR CONNECTION TO A BATTERY; (C) A SILICON CONTROLLED RECTIFIER SERIALLY CONNECTED BETWEEN SAID INPUT AND OUTPUT TERMINALS; (D) A FIRST RESISTANCE VOLTAGE DIVIDER CONNECTED SERIALLY THROUGH A HALF-WAVE RECTIFIER TO SAID INPUT TERMINALS; (E) A FIRST UNIJUNCTION TRANSISTOR HAVING ITS EMITTER AND ONE BASE ELECTRODE CONNECTED AT OPPOSITE ENDS OF SAID FIRST VOLTAGE DIVIDER AND ITS REMAINING BASE ELECTRODE CONNECTED TO THE CONTROL ELECTRODE OF SAID SILICON CONTROLLED RECTIFIER; (F) A RESISTANCE-CAPACITOR CHARGING CIRCUIT CONNECTED ACROSS SAID FIRST DIVIDER AND TO THE EMITTER OF SAID UNIJUNCTION TRANSISTOR TO DELAY EACH FIRING OF SAID SILICON CONTROLLED RECTIFIER, THE RESISTANCE OF SAID CHARGING CIRCUIT INCLUDING A SECOND SERIES TRANSISTOR HAVING FIRST AND SECOND ELECTRODES IN THE CHARGING PATH AND A THIRD ELECTRODE CONNECTED TO AN INTERMEDIATE TAP IN SAID FIRST VOLTAGE DIVIDER; (G) AND A TRANSISTORIZED OVERVOLTAGE TRIP CIRCUIT MEANS WITH AN INPUT COUPLED TO SAID OUTPUT CHARGING TERMINALS AND AN OUTPUT COUPLED TO SAID INTERMEDIATE TAP ON SAID FIRST VOLTAGE DIVIDER TO PROVIDE A CUT-OFF POTENTIAL TO SAID SERIES TRANSISTOR WHEN THE VOLTAGE OF SAID CHARGING TERMINALS EXCEEDS A PRESELECTED SAFE VALUE.
Claim 2
Dependent Claim
206 words
A BATTERY CHARGER COMPRISING; (A) A PAIR OF INPUT TERMINALS FOR CONNECTION TO AN ALTERNATING CURRENT SOURCE; (B) A PAIR OF OUTPUT CHARGING TERMINALS FOR CONNECTION TO A BATTERY; (C) A SILICON CONTROLLED RECTIFIER SERIALLY CONNECTED BETWEEN SAID INPUT AND OUTPUT TERMINALS; (D) A FIRST RESISTANCE VOLTAGE DIVIDER CONNECTED SERIALLY THROUGH A HALF-WAVE RECTIFIER TO SAID INPUT TERMINALS; (E) A FIRST UNIJUNCTION TRANSISTOR HAVING ITS EMITTER AND ONE BASE ELECTRODE CONNECTED AT OPPOSITE ENDS OF SAID FIRST VOLTAGE DIVIDER AND ITS REMAINING BASE ELECTRODE CONNECTED TO THE CONTROL ELECTRODE OF SAID SILICON CONTROLLED RECTIFIER; (F) A RESISTANCE-CAPACITOR CHARGING CIRCUIT CONNECTED ACROSS SAID FIRST DIVIDER AND TO THE EMITTER OF SAID UNIJUNCTION TRANSISTOR TO DELAY EACH FIRING OF SAID SILICON CONTROLLED RECTIFIER, THE RESISTANCE OF SAID CHARGING CIRCUIT INCLUDING A SECOND SERIES TRANSISTOR HAVING FIRST AND SECOND ELECTRODES IN THE CHARGING PATH AND A THIRD ELECTRODE CONNECTED TO AN INTERMEDIATE TAP IN SAID FIRST VOLTAGE DIVIDER; (G) AND A TRANSISTORIZED OVERVOLTAGE TRIP CIRCUIT MEANS WITH AN INPUT COUPLED TO SAID OUTPUT CHARGING TERMINALS AND AN OUTPUT COUPLED TO SAID INTERMEDIATE TAP ON SAID FIRST VOLTAGE DIVIDER TO PROVIDE A CUT-OFF POTENTIAL TO SAID SERIES TRANSISTOR WHEN THE VOLTAGE OF SAID CHARGING TERMINALS EXCEEDS A PRESELECTED SAFE VALUE.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1967-12-08 | 1968-06-08 | 1968-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1971-12-08 | 1972-06-08 | 1972-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1975-12-08 | 1976-06-08 | 1976-12-08 | $7700.00 | Window Closed / Lapsed |