Pulse train sensing circuitry

Claim 1

IN AN ELECTRONIC DIGITAL COMPUTER, APPARATUS FOR PERFORMING ARITHMETIC OPERATIONS COMPRISING FIRST REGISTER MEANS HAVING A PLURALITY OF STAGES FOR STORING BINARY SIGNALS REPRESENTATIVE OF A FIRST VALUE, SECOND REGISTER MEANS HAVING A CORRESPONDING NUMBER OF STAGES FOR STORING BINARY SIGNALS REPRESENTATIVE OF A SECOND VALUE, MEANS INCLUDING AN ADDER HAVING A CORRESPONDING NUMBER OF STAGES TO PERFORM A SUMMING OPERATION ON THE NUMBERS HELD IN SAID FIRST AND SECOND REGISTERS, EACH ADDER STAGE HAVING A CARRY GATE CONNECTED THERETO FOR PASSING A CARRY PULSE GENERATED BY THAT STAGE DURING THE SUMMING OPERATION, SAID SUMMING OPERATION PRODUCING A SERIAL TRAIN OF CARRY PULSES OVERLAPPING IN TIME, AND MEANS TO DETECT A CHANGE IN SAID SERIAL TRAIN OF CARRY PULSES PRODUCED DURING SAID SUMMING OPERATION COMPRISING A DIODE CORRESPONDING TO EACH STAGE OF SAID ADDER, EACH SAID DIODE HAVING FIRST AND SECOND TERMINALS, ONE OF SAID TERMINALS OF EACH DIODE BEING CONNECTED TO THE OUTPUT OF THE CARRY GATE OF THE ASSOCIATED ADDER STAGE TO SENSE GENERATED CARRY PULSES AND THE OTHER TERMINAL BEING CONNECTED TO THE LIKE TERMINALS OF THE OTHER DIODES IN A COMMON CIRCUIT SO THAT CARRY PULSES GENERATED BY SAID ADDER ARE APPLIED TO SAID COMMON CIRCUIT AND PROVIDE A LEVEL OUTPUT INDICATIVE OF CARRY PROPAGATION, AND SIGNAL GENERATING MEANS FOR CONVERTING A TRANSITION IN SAID LEVEL OUTPUT TO A PULSE SIGNAL INDICATIVE OF TERMINATION OF CARRY PROPAGATION IN SAID ADDER INCLUDING A TRANSISTOR HAVING EMITTER, BASE, AND COLLECTOR ELECTRODES, SAID TRANSISTOR BEING CONNECTED IN COMMON EMITTER CONFIGURATION, A PULSE TRANSFORMER CONNECTED TO THE COLLECTOR ELECTRODE OF SAID TRANSISTOR, AND MEANS TO APPLY SAID LEVEL OUTPUT TO THE BASE ELECTRODE OF SAID TRANSISTOR SO THAT A TRANSITION IN SAID LEVEL OUTPUT CAUSES SAID TRANSISTOR TO CHANGE ITS STATE OF CONDUCTION AND CAUSES SAID PULSE TRANSFORMER TO PRODUCE A PULSE SIGNAL INDICATIVE OF THE COMPLETION OF A SUMMING OPERATION AT THAT TIME.