Bistable transistor circuit with ferroelectric memory element

Claim 1

AN ELECTRICAL CIRCUIT COMPRISING: A PAIR OF TRANSISTORS EACH HAVING AN EMITTER, A COLLECTOR, AND A BASE; A PAIR OF BIAS CIRCUITS EACH CONNECTED TO A SEPARATE ONE OF SAID TRANSISTOR BASES, THE COLLECTOR OF EACH TRANSISTOR BEING CONNECTED TO THE BIAS CIRCUIT OF THE OTHER TRANSISTOR TO DEFINE A BISTABLE CIRCUIT SUCH THAT EITHER OF SAID TRANSISTORS MAY BE IN A HIGH CONDUCTION STATE BUT NOT BOTH SIMULTANEOUSLY; A FERROELECTRIC CAPACITOR CONNECTED ACROSS THE COLLECTORS OF SAID TRANSISTORS AND CONNECTED TO SAID BIAS CIRCUITS TO ACQUIRE A CHARGE THE POLARITY OF WHICH DEPENDS ON THE RELATIVE CONDUCTANCES OF SAID TRANSISTORS AND TO RETAIN A REMANENT CHARGE IN THE EVENT OF INTERRUPTION OF POWER TO SAID CIRCUIT, WHEREBY A SHIFT IN THE HIGH CONDUCTION STATE FROM ONE TRANSISTOR TO THE OTHER OCCASIONS A FLOW OF CAPACITIVE CURRENT IN SAID FERROELECTRIC CAPACITOR; AND IMPEDANCE MEANS CONNECTED TO SAID BIAS CIRCUITS RESPONSIVE TO SAID CAPACITIVE CURRENT UPON RESTORATION OF POWER TO THE CIRCUIT TO INHIBIT CONDUCTION OF THE TRANSISTOR NOT HIGHLY CONDUCTING BEFORE INTERRUPTION OF POWER.