Simulated high-q inductor

Claim 1

A HIGH-Q INDUCTANCE SIMULATING CIRCUIT, COMPRISING A TRANSISTOR HAVING AN INPUT ELECTRODE, AN OUTPUT ELECTRODE, AND AN ELECTRODE COMMON TO THE CIRCUITS OF SAID INPUT AND OUTPUT ELECTRODES, RESISTANCE MEANS CONNECTED BETWEEN SAID INPUT AND OUTPUT ELECTRODES TO PROVIDE SIGNAL COUPLING THEREBETWEEN, CAPACITIVE MEAN INCLUDED IN THE INPUT CIRCUIT BETWEEN SAID INPUT ELECTRODE AND SAID COMMON ELECTRODE, AN OUTPUT LOAD IN CIRCUIT WITH SAID OUTPUT ELECTRODE AND SAID COMMON ELECTRODE, SAID CIRCUIT AS THUS FAR DEFINED TENDING TO SIMULATE A LOW-Q INDUCTOR BY REASON OF THE FACT THAT THE OUTPUT CURRENT TENDS TO LAG THE OUTPUT ELECTRODE VOLTAGE BY AN ANGLE OF LAG SUBSTANTIALLY LESS THAN 90*, AND MEANS FOR IMPARTING HIGH Q TO SAID CIRCUIT COMPRISING LOW-Q INDUCTIVE MEANS CONNECTED TO SAID COMMON ELECTRODE AND IN COMON CIRCUIT WITH SAID INPUT AND OUTPUT ELECTRODES FOR INCREASING SAID ANGLE OF LAG, SAID INDUCTIVE MEANS COMPRISING A TRANSISTOR CIRCUIT SIMULATING A LOW-Q INDUCTOR.