US3152299A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistorized power control circuits
Assignee: GTE Sylvania Inc
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Filing: 1960-08-23
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Granted: 1964-10-06
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Expires: 1980-08-23
Abstract
No abstract record available.
Inventors
- 👤 Thomas F Leney
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 00:35
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/12; G05F1/40; G05F1/44; G05F1/445
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
169 words
A CIRCUIT FOR REGULATING THE POWER DELIVERED TO A LOAD FROM A SOURCE OF ALTERNATING CURRENT POTENTIAL HAVING FIRST AND SECOND OUTPUT TERMINALS, SAID CIRCUIT COMPRISING, A CONNECTION FROM SAID FIRST OUTPUT TERMINAL TO ONE TERMINAL OF SAID LOAD, FIRST AND SECOND PARALLEL CONDUCTION PATHS CONNECTED BETWEEN THE OTHER TERMINAL OF SAID LOAD AND SAID SECOND OUTPUT TERMINAL, EACH OF SAID PATHS COMPRISING A FIRST DIODE, A TRANSISTOR HAVING COLLECTOR, EMITTER AND BASE ELECTRODES, AND A SECOND DIODE BEING CONNECTED TO THE COLLECTOR OF THE TRANSISTOR AND THE ANODE OF SAID SECOND DIODE BEING CONNECTED TO THE EMITTER OF THE TRANSISTOR IN ITS CORRESPONDING CONDUCTION PATH, THE ANODE OF SAID FIRST DIODE IN SAID FIRST CONDUCTION PATH BEING CONNECTED TO SAID OTHER TERMINAL OF SAID LOAD AND THE ANODE OF SAID FIRST DIODE IN SAID SECOND CONDUCTION PATH BEING CONNECTED TO SAID SECOND OUTPUT TERMINAL, MEANS TO APPLY A FORWARD BIASING POTENTIAL TO THE EMITTER OF BOTH SAID TRANSISTORS, MEANS TO APPLY SUBSTANTIALLY EQUAL DIRECT CURRENT POTENTIALS TO THE
Claim 2
Dependent Claim
169 words
A CIRCUIT FOR REGULATING THE POWER DELIVERED TO A LOAD FROM A SOURCE OF ALTERNATING CURRENT POTENTIAL HAVING FIRST AND SECOND OUTPUT TERMINALS, SAID CIRCUIT COMPRISING, A CONNECTION FROM SAID FIRST OUTPUT TERMINAL TO ONE TERMINAL OF SAID LOAD, FIRST AND SECOND PARALLEL CONDUCTION PATHS CONNECTED BETWEEN THE OTHER TERMINAL OF SAID LOAD AND SAID SECOND OUTPUT TERMINAL, EACH OF SAID PATHS COMPRISING A FIRST DIODE, A TRANSISTOR HAVING COLLECTOR, EMITTER AND BASE ELECTRODES, AND A SECOND DIODE BEING CONNECTED TO THE COLLECTOR OF THE TRANSISTOR AND THE ANODE OF SAID SECOND DIODE BEING CONNECTED TO THE EMITTER OF THE TRANSISTOR IN ITS CORRESPONDING CONDUCTION PATH, THE ANODE OF SAID FIRST DIODE IN SAID FIRST CONDUCTION PATH BEING CONNECTED TO SAID OTHER TERMINAL OF SAID LOAD AND THE ANODE OF SAID FIRST DIODE IN SAID SECOND CONDUCTION PATH BEING CONNECTED TO SAID SECOND OUTPUT TERMINAL, MEANS TO APPLY A FORWARD BIASING POTENTIAL TO THE EMITTER OF BOTH SAID TRANSISTORS, MEANS TO APPLY SUBSTANTIALLY EQUAL DIRECT CURRENT POTENTIALS TO THE
References Cited (Backward Citations)
US2813244A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1967-10-06 | 1968-04-06 | 1968-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1971-10-06 | 1972-04-06 | 1972-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1975-10-06 | 1976-04-06 | 1976-10-06 | $7700.00 | Window Closed / Lapsed |