← Back to Patent Explorer
US3149289A Expired / Lapsed US ⏱️ 0.0 years remaining

Signal generator

Assignee: Individual
•
Filing: 1957-01-16
•
Granted: 1964-09-15
•
Expires: 1977-01-16
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

No abstract record available.

Inventors

  • 👤 Bernard W Moss

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 19:08
CPC Classifications
G; G01; G01S; G01S7/00; G01S7/02; G01S7/40; G01S7/4052; G01S7/4082; G01S7/4095

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 168 words
A SIGNAL GENERATOR COMPRISING, A FIRST OSCILLATOR INCLUDING KEYING MEANS, A SECOND OSCILLATOR INCLUDING KEYING MEANS, THE KEYING MEANS FOR SAID FIRST AND SAID SECOND OSCILLATORS BEING ARRANGED TO RECEIVE A COMMON KEYING SIGNAL, SAID FIRST AND SAID SECOND OSCILLATORS COMMENCING OPERATION IN OPPOSITE PHASE UPON RECEPTION OF A KEYING SIGNAL, MEANS FOR ADDING THE OUTPUTS OF SAID FIRST AND SAID SECOND OSCILLATORS TO PROVIDE A SUM VOLTAGE, A THIRD OSCILLATOR INCLUDING KEYING MEANS, A FOURTH OSCILLATOR INCLUDING KEYING MEANS, A FIRST BALANCED MODULATOR RECEIVING THE OUTPUTS OF SAID THIRD AND SAID FOURTH OSCILLATORS AND PROVIDING A COMPLEX OUTPUT VOLTAGE, MEANS FOR ELIMINATING UNDESIRED COMPONENTS FROM THE OUTPUT OF SAID FIRST BALANCED MODULATOR, AND FOR PASSING A DESIRED COMPONENT, A SECOND BALANCED MODULATOR RECEIVING SAID SUM VOLTAGE AND THE DESIRED COMPONENT OF SAID FIRST BALANCED MODULATOR OUTPUT AND PROVIDING A SECOND COMPLEX VOLTAGE OUTPUT, AND MEANS FOR ELIMINATING UNDESIRED COMPONENTS FROM SAID SECOND COMPLEX VOLTAGE AND FOR PASSING THE DESIRED COMPONENT CONSTITUTING THE OUTPUT OF THE SIGNAL GENERATOR.
Claim 2
Dependent Claim 168 words
A SIGNAL GENERATOR COMPRISING, A FIRST OSCILLATOR INCLUDING KEYING MEANS, A SECOND OSCILLATOR INCLUDING KEYING MEANS, THE KEYING MEANS FOR SAID FIRST AND SAID SECOND OSCILLATORS BEING ARRANGED TO RECEIVE A COMMON KEYING SIGNAL, SAID FIRST AND SAID SECOND OSCILLATORS COMMENCING OPERATION IN OPPOSITE PHASE UPON RECEPTION OF A KEYING SIGNAL, MEANS FOR ADDING THE OUTPUTS OF SAID FIRST AND SAID SECOND OSCILLATORS TO PROVIDE A SUM VOLTAGE, A THIRD OSCILLATOR INCLUDING KEYING MEANS, A FOURTH OSCILLATOR INCLUDING KEYING MEANS, A FIRST BALANCED MODULATOR RECEIVING THE OUTPUTS OF SAID THIRD AND SAID FOURTH OSCILLATORS AND PROVIDING A COMPLEX OUTPUT VOLTAGE, MEANS FOR ELIMINATING UNDESIRED COMPONENTS FROM THE OUTPUT OF SAID FIRST BALANCED MODULATOR, AND FOR PASSING A DESIRED COMPONENT, A SECOND BALANCED MODULATOR RECEIVING SAID SUM VOLTAGE AND THE DESIRED COMPONENT OF SAID FIRST BALANCED MODULATOR OUTPUT AND PROVIDING A SECOND COMPLEX VOLTAGE OUTPUT, AND MEANS FOR ELIMINATING UNDESIRED COMPONENTS FROM SAID SECOND COMPLEX VOLTAGE AND FOR PASSING THE DESIRED COMPONENT CONSTITUTING THE OUTPUT OF THE SIGNAL GENERATOR.

References Cited (Backward Citations)

US2751689A Cited
US2555373A Cited
US2656465A Cited
US2567410A Cited
US2781450A Cited
US2786140A Cited
US2848616A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1967-09-15 1968-03-16 1968-09-15 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1971-09-15 1972-03-16 1972-09-15 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1975-09-15 1976-03-16 1976-09-15 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag