Synchronously operated transistor switching circuit

Claim 1

A SYNCHRONIZED DELAY CIRCUIT OF THE CLASS DESCRIBED COMPRISING, A TRANSISTOR HAVING EMITTER, BASE AND COLLECTOR ELECTRODES, A SOURCE OF BIAS VOLTAGE HAVING A VOLTAGE DIVIDER NETWORK CONNECTED TO SAID BASE ELECTRODE FOR RENDERING SAID TRANSISTOR NORMALLY NON-CONDUCTING, AND INDUCTIVE ELEMENT IN CIRCUIT WITH SAID DIVIDER NETWORK AND ADAPTED TO STORE ELECTRICAL ENERGY, A SOURCE OF INPUT PULSES, A FIRST BRANCH CIRCUIT CONNECTING SAID INPUT PULSES SOURCE WITH SAID INDUCTIVE ELEMENT AND INCLUDING GATING MEANS, A SOURCE OF SYNC PULSES, AND A SECOND BRANCH CIRCUIT CONNECTING SAID SYNC PULSE SOURCE WITH SAID GATING MEANS AND INCLUDING SIGNAL COUPLING MEANS, THE PRESENCE OF AN INPUT PULSE FOLLOWED BY A SYNC PULSE CONDITIONING SAID GATING MEANS TO CAUSE CURRENT FLOW IN SAID INDUCTIVE ELEMENT AND SAID FIRST BRACH CIRCUIT, THE TERMINATION OF SAID SYNC PULSE SERVING TO DECOUPLE SAID GATING MEANS TO DISCHARGE ELECTRICAL ENERGY STORED IN SAID INDUCTIVE ELEMENT AS CURRENT FLOW IN THE BASE CIRCUIT OF SAID TRANSISTOR TO PRODUCE A DELAYED OUTPUT PULSE AT SAID COLLECTOR ELECTRODE.