Digital data comparator utilizing majority-decision logic circuits

Claim 1

FOR COMPARING BINARY-CODED DATA STORED IN TWO BINARY REGISTERS OF AN EQUAL NUMBER OF CORRESPONDING DIGIT ORDER STAGES: A THREE-INPUT MAJORITY-DECISION LOGIC CIRCUIT FOR EACH DIGIT ORDER OF THE INFORMATION TO BE COMPARED; MEANS FOR COUPLING SIGNAL REPRESENTATIONS OF THE BINARY VALUE OF EACH STAGE OF ONE OF SAID REGISTERS TO A FIRST INPUT OF A DIFFERENT ONE OF SAID MAJORITY-DECISION LOGIC CIRCUITS;; MEANS FOR COUPLING SIGNAL REPRESENTATIONS OF THE COMPLEMENT OF THE BINARY VALUE OF EACH STAGE OF THE OTHER OF SAID REGISTERS TO A SECOND INPUT OF SAID CORRESPONDING DIGIT ORDER MAJORITY-DECISION LOGIC CIRCUIT; EACH OF SAID LOGIC CIRCUITS INCLUDING MEANS FOR DEVELOPING AN OUTPUT SIGNAL REPRESENTING A FIRST BINARY VALUE WHEN BOTH OF SAID FIRST AND SECOND INPUT SIGNALS ARE OF SAID FIRST BINARY VALUE AND FOR DEVELOPING AN OUTPUT SIGNAL REPRESENTING A SECOND BINARY VALUE WHEN EITHER OF SAID FIRST OR SECOND INPUTS ARE OF SAID SECOND BINARY VALUE WHEREBY SAID MAJORITY-DECISION LOGIC CIRCUITS COMPARE SAID DATA DIGIT-BY-DIGIT; UNIDIRECTIONAL CONDUCTING MEANS FOR COUPLING SAID OUTPUT SIGNALS RESULTING FROM SAID DIGIT-BY-DIGIT COMPARISON FROM EACH OF SAID LOGIC CIRCUITS TO THE THIRD INPUT OF THE NEXT HIGHER DIGIT ORDER MAJORITY-DECISION LOGIC CIRCUIT; EACH OF SAID LOGIC CIRCUITS FURTHER INCLUDING MEANS FOR COMBINING SAID THIRD INPUT SIGNAL WITH SAID FIRST AND SECOND INPUT SIGNALS AND FOR DEVELOPING AN OUTPUT SIGNAL IN RESPONSE TO SAID COMBINED SIGNALS OF SAID FIRST BINARY VALUE WHEN ANY TWO OF SAID FIRST, SECOND AND THIRD INPUT SIGNALS ARE OF SAID FIRST BINARY VALUE, THE OUTPUT SIGNAL OF SAID HIGHEST DIGIT ORDER MAJORITY-DECISION LOGIC CIRCUIT REPRESENTATIVE OF SAID FIRST BINARY VALUE WHEN SAID BINARY INFORMATION IN SAID FIRST REGISTER IS OF AT LEAST EQUAL IN MAGNITUDE TO THAT OF SAID OTHER REGISTER.