Quadrature eliminator and selectrive lag circuit using a single rectifier ring and half wave discriminator modulator action

Claim 1

A QUADRATURE SIGNAL ELIMINATOR AND SELECTIVE LAG CIRCUIT COMPRISING: IN COMBINATION, A CENTER-TAPPED CIRCUIT ADAPTED TO BE ENERGIZED BY A SOURCE OF PERIODICALLY VARYING REFERENCE POTENTIAL; A FIRST PAIR OF RECTIFIER ELEMENTS CONNECTED IN SERIES ACROSS SAID REFERENCE POTENTIAL CIRCUIT AND POLED IN A SINGLE CURRENT-CARRYING DIRECTION; A SECOND PAIR OF RECTIFIER ELEMENTS CONNECTED IN SERIES ACROSS SAID REFERENCE POTENTIAL SOURCE AND POLED IN AN OPPOSITE CURRENT-CARRYING DIRECTION TO THAT OF SAID FIRST PAIR; MEANS TO CONNECT A SOURCE OF INPUT SIGNALS CONTAINING UNDESIRED SIGNAL COMPONENTS AT PHASE QUADRATURE TO SAID REFERENCE POTENTIAL; CAPACITANCE MEANS; AND LOAD IMPEDANCE MEANS, SAID INPUT SIGNAL SOURCE AND SAID CAPACITANCE MEANS BEING CONNECTED IN SERIES DIRECTLY BETWEEN A POINT BETWEEN SAID FIRST PAIR OF RECTIFIER ELEMENTS AND THE CENTER TAP OF SAID REFERENCE POTENTIAL SOURCE IN THAT ORDER, AND SAID LOAD IMPEDANCE MEANS AND SAID CAPACITANCE MEANS BEING CONNECTED IN SERIES DIRECTLY BETWEEN A POINT BETWEEN SAID SECOND PAIR OF RECTIFIER ELEMENTS AND THE CENTER TAP OF SAID REFERENCE POTENTIAL SOURCE IN THAT ORDER, SUCH THAT SAID FIRST PAIR OF RECTIFIER ELEMENTS OPERATES AS A DISCRIMINATOR TO CHARGE SAID CAPACITANCE MEANS FROM ALL BUT THE QUADRATURE COMPONENTS OF SAID INPUT SIGNAL AND SAID SECOND PAIR OF RECTIFIER ELEMENTS ACTS AS A MODULATOR OF THE POTENTIAL ACROSS SAID CAPACITANCE MEANS, SUPPLYING TO SAID LOAD IMPEDANCE AN OUTPUT SIGNAL RELATIVELY FREE OF SAID UN-