Switching circuits

Claim 1

A GATE CIRCUIT COMPRISING FIRST AND SECOND TRANSISTORS OF OPPOSITE CONDUCTIVITY TYPES EACH HAVING BASE, EMITTER AND COLLECTOR ELECTRODES, SEPARATE MEANS RESPECTIVELY CONNECTING THE EMITTER ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS THROUGH FIRST AND SECOND RESISTORS TO FIRST AND SECOND SOURCES OF POTENTIAL, RESPECTIVELY, SAID FIRST SOURCE OF POTENTIAL BEING POSITIVE RELATIVE TO SAID SECOND SOURCE, SEPARATE MEANS CONNECTING THE COLLECTOR ELECTRODES OF SAID FIRST AND SECOND TRANSISTORS TO SAID SECOND AND SAID FIRST SOURCES OF POTENTIAL, RESPECTIVELY, MEANS DIRECTLY CONNECTING THE EMITTER ELECTRODE OF SAID FIRST TRANSISTOR TO THE BASE ELECTRODE OF SAID SECOND TRANSISTOR, AN OUTPUT TERMINAL CONNECTED TO THE EMITTER ELECTRODE OF SAID SECOND TRANSISTOR, AND MEANS CONNECTED TO THE EMITTER ELECTRODE OF SAID FIRST TRANSISTOR AND THE BASE ELECTRODE OF SAID SECOND TRANSISTOR FOR APPLYING THERETO A PULSE OF SUFFICIENT AMPLITUDE SIMULTANEOUSLY TO CAUSE BOTH SAID TRANSISTORS TO CONDUCT FOR THE PERIOD OF THE PULSE TO THEREBY TRANSMIT TO SAID OUTPUT TERMINAL, DURING THE PULSE PERIOD, A SIGNAL APPLIED TO THE BASE ELECTRODE OF SAID FIRST TRANSISTOR.