Checking circuitry for information handling apparatus

Claim 1

CHECKING APPARATUS FOR A DATA PROCESSOR COMPRISING AN INPUT DIGITAL SIGNAL SOURCE, A TRANSFER CIRCUIT HAVING AN INPUT AND AN OUTPUT, SAID TRANSFER CIRCUIT BEING ADAPTED TO TRANSFER A PLURALITY OF BITS OF DIGITAL DATA, AN OUTPUT UTILIZATION CIRCUIT, MEANS CONNECTING THE INPUT OIF SAID TRANSFER CIRCUIT TO SAID DIGITAL SIGNAL SOURCE AND THE OUTPUT OF SAID TRANSFER CIRCUIT TO SAID OUTPUT UTILIZATION CIRCUIT, A FIRST BISTABLE CHECKING REGISTER CONNECTED TO SAID SIGNAL SOURCE, A SECOND BISTABLE CHEWCKING REGISTER CONNECTED TO SAID OUTPUT OF SAID TRANSFER CIRCUIT, SAID FIRST AND SECOND REGISTERS BEING ADAPTED TO BE SET BY EACH ONE OF THE LIKE BITS OF DIGITAL DATA, AND COMPARISON MEANS CONNECTED TO SAID REGISTERS TO PRODUCE AN OUTPUT SIGNAL INDICATIVE OF A LACK OF BISTABLE IDENTITY OF OUTPUT FROM SAID REGISTERS UPON THE TRANSFER OF EACH BIT THROUGH SAID TRANSFER CIRCUIT.