US3089968A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-linear amplifier
Assignee: General Precision Inc
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Filing: 1961-06-22
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Granted: 1963-05-14
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Expires: 1981-06-22
Abstract
No abstract record available.
Inventors
- 👤 Dale W Dunn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 05:35
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/24
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
163 words
ANTI-LOGARITHMIC CIRCUITRY COMPRISING: A TRANSISTOR HAVING A BASE, COLLECTOR, AN EMITTER; A COMMON LINE COMMON TO THE INPUT AND OUTPUT OF THE ANTI-LOGARITHM CIRCUITRY: SIGNAL INPUT MEANS COUPLED TO THE BASE OF SAID TRANSISTOR; VARYING EMITTER CIRCUIT RESISTANCE MEANS COUPLED BETWEEN THE EMITTER OF SAID TRANSISTOR AND SAID COMMON LINE, SAID RESISTANCE MEANS COMPRISING AT LEAST ONE SEMICONDUCTOR DIODE IN WHICH THE RESISTANCE DECREASES LOGARITHMICALLY WITH INCREASE IN VOLTAGE APPLIED ACROSS IT; AND COLLECTOR CIRCUIT MEANS INCLUDING OUTPUT CIRCUITRY AND VOLTAGE POTENTIAL CIRCUITRY COUPLED BETWEEN THE COLLECTOR OF SAID TRANSISTOR AND SAID COMMON LINE, SAID COLLECTOR CIRCUIT MEANS HAVING TOTAL CIRCUIT RESISTANCE OF LESS THAN A PRODUCT OF SAID VARYING EMITTER CIRCUIT RESISTANCE MEANS AND THE BETA CHARACTERISTIC OF SAID TRANSISTOR WHEREBY SAID TRANSISTOR WILL PRODUCE AN OUTPUT SIGNAL PROPORTIONAL TO THE RATIO OF TOTAL CIRCUIT RESISTANCE IN SAID COLLECTOR CIRCUIT MEANS TO SAID VARYING EMITTER CIRCUIT RESISTANCE MEANS AND PROPORTIONAL TO THE ANTI-LOGARITHM OF THE SIGNAL INTRODUCED TO SAID SIGNAL INPUT MEANS.
Claim 2
Dependent Claim
163 words
ANTI-LOGARITHMIC CIRCUITRY COMPRISING: A TRANSISTOR HAVING A BASE, COLLECTOR, AN EMITTER; A COMMON LINE COMMON TO THE INPUT AND OUTPUT OF THE ANTI-LOGARITHM CIRCUITRY: SIGNAL INPUT MEANS COUPLED TO THE BASE OF SAID TRANSISTOR; VARYING EMITTER CIRCUIT RESISTANCE MEANS COUPLED BETWEEN THE EMITTER OF SAID TRANSISTOR AND SAID COMMON LINE, SAID RESISTANCE MEANS COMPRISING AT LEAST ONE SEMICONDUCTOR DIODE IN WHICH THE RESISTANCE DECREASES LOGARITHMICALLY WITH INCREASE IN VOLTAGE APPLIED ACROSS IT; AND COLLECTOR CIRCUIT MEANS INCLUDING OUTPUT CIRCUITRY AND VOLTAGE POTENTIAL CIRCUITRY COUPLED BETWEEN THE COLLECTOR OF SAID TRANSISTOR AND SAID COMMON LINE, SAID COLLECTOR CIRCUIT MEANS HAVING TOTAL CIRCUIT RESISTANCE OF LESS THAN A PRODUCT OF SAID VARYING EMITTER CIRCUIT RESISTANCE MEANS AND THE BETA CHARACTERISTIC OF SAID TRANSISTOR WHEREBY SAID TRANSISTOR WILL PRODUCE AN OUTPUT SIGNAL PROPORTIONAL TO THE RATIO OF TOTAL CIRCUIT RESISTANCE IN SAID COLLECTOR CIRCUIT MEANS TO SAID VARYING EMITTER CIRCUIT RESISTANCE MEANS AND PROPORTIONAL TO THE ANTI-LOGARITHM OF THE SIGNAL INTRODUCED TO SAID SIGNAL INPUT MEANS.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1966-05-13 | 1966-11-12 | 1967-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1970-05-13 | 1970-11-12 | 1971-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1974-05-13 | 1974-11-12 | 1975-05-14 | $7700.00 | Window Closed / Lapsed |