Cryogenic memory system

Claim 1

IN A SUPERCONDUCTOR MEMORY INCLUDING A PLURALITY OF SUPERCONDUCTOR STORAGE DEVICES EACH CAPABLE OF ASSUMING AT LEAST FIRST AND SECOND DIFFERENT STABLE INFORMATION REPRESENTING STATES; EACH OF SAID STORAGE DEVICES INCLUDING INPUT AND OUTPUT MEANS; FIRST, SECOND, THIRD AND FOURTH SUPERCONDUCTOR CURRENT PATHS CONNECTED IN PARALLEL ACROSS A CURRENT SOURCE; EACH OF SAID SUPERCONDUCTOR PATHS BEING MAINTAINED AT A SUPERCONDUCTIVE TEMPERATURE; SAID THIRD SUPERCONDUCTOR CURRENT PATH BEING ARRANGED ADJACENT THE OUTPUT MEANS OF EACH OF SAID STORAGE DEVICES; SAID FOURTH SUPERCONDUCTOR CURRENT PATH BEING ARRANGED ADJACENT THE INPUT MEANS OF EACH OF SAID STORAGE DEVICES; AND MEANS FOR CONTROLLING READ AND WRITE OPERATIONS IN SAID MEMORY COMPRISING FIRST, SECOND, THIRD AND FOURTH CONTROL CONDUCTOR MEANS EACH ARRANGED ADJACENT A CORRESPONDING ONE OF SAID FIRST, SECOND, THIRD AND FOURTH CURRENT PATHS AND EFFECTIVE WHEN ENERGIZED TO INTRODUCE RESISTANCE INTO THE CORRESPONDING ONE OF SAID PATHS; EACH OF SAID FIRST, SECOND, THIRD AND FOURTH CONTROL CONDUCTORS BEING INITIALLY ENERGIZED FOR BOTH READ AND WRITE OPERATIONS AND THEN SAID THIRD CONTROL CONDUCTOR BEING DEENERGIZED, SAID FIRST AND SECOND CONTROL CONDUCTORS BEING DEENERGIZED, SAID THIRD CONTROL CONDUCTOR BEING ENERGIZED, AND SAID THIRD AND FOURTH CONTROL CONDUCTORS BEING DEENERGIZED IN THAT ORDER FOR A READ OPERATION, OR SAID FOURTH CONTROL CONDUCTOR BEING DEENERGIZED, SAID FIRST AND SECOND CONDUCTORS BEING DEENERGIZED, SAID FOURTH CONTROL CONDUCTOR BEING ENERGIZED, AND SAID THIRD AND FOURTH CONTROL CONDUCTORS BEING DEENERGIZED IN THAT ORDER FOR A WRITE OPERATION.