Means for measuring and testing components

Claim 1

A METHOD OF TESTING A PLURALITY OF SIMILAR ELECTRICAL ELEMENTS BY SUBJECTING SAID ELEMENTS OF FIRST AND SECOND CONDITIONS WHICH METHOD INCLUDES THE STEPS OF ARRANGING SAID ELEMENTS TO FORM A CONFIGURATION IN WHICH THE LOCATION OF EACH ELEMENT IS UNIQUELY IDENTIFIED BY A PLURALITY OF COORDINATE VALUES, CONNECTING TOGETHER ADJACENT ELEMENTS IN SAID CONFIGURATION, THERE BEING FORMED SUBCOMBINATIONS OF SAID CONFIGURATION WHOSE LOCATION IS IDENTIFIED BY A COMMON ONE OF SAID COORDINATE VALUES, INTERCOUPLING SAID SUBCOMBINATIONS TO FORM A FIRST ARRANGEMENT, SUBJECTING SAID FIRST ARRANGEMENT TO SAID FIRST CONDITION, INTERCOUPLING THE SAID SUBCOMBINATIONS TO FORM A SECOND ARRANGEMENT, AND SUBJECTING SAID SECOND ARRANGEMENT TO SAID SECOND CONDITION, SAID ELEMENTS EACH COMPRISING AT LEAST ONE SEMICONDUCTOR RECTIFYING JUNCTION, SAID COORDINATE VALUES COMPRISING A ROW NUMBER AND COLUMN NUMBER, EACH ROW AND EACH COLUMN OF SAID JUNCTIONS COMPRISING RESPECTIVE ONES OF SAID COMBINATIONS, SAID RECTIFYING JUNCTIONS IN A SUBCOMBINATION BEING POLED IN THE SAME SENSE AND COMPRISING A SERIES COMBINATION, SAID FIRST AND SECOND CONDITIONS BEING THE APPLICATION OF FORWARD BIASING POTENTIALS AND REVERSE BIASING POTENTIALS RESPECTIVELY ACROSS JUNCTIONS IN A SUBCOMBINATION.

Claim 2

A METHOD OF TESTING A PLURALITY OF SIMILAR ELECTRICAL ELEMENTS BY SUBJECTING SAID ELEMENTS OF FIRST AND SECOND CONDITIONS WHICH METHOD INCLUDES THE STEPS OF ARRANGING SAID ELEMENTS TO FORM A CONFIGURATION IN WHICH THE LOCATION OF EACH ELEMENT IS UNIQUELY IDENTIFIED BY A PLURALITY OF COORDINATE VALUES, CONNECTING TOGETHER ADJACENT ELEMENTS IN SAID CONFIGURATION, THERE BEING FORMED SUBCOMBINATIONS OF SAID CONFIGURATION WHOSE LOCATION IS IDENTIFIED BY A COMMON ONE OF SAID COORDINATE VALUES, INTERCOUPLING SAID SUBCOMBINATIONS TO FORM A FIRST ARRANGEMENT, SUBJECTING SAID FIRST ARRANGEMENT TO SAID FIRST CONDITION, INTERCOUPLING THE SAID SUBCOMBINATIONS TO FORM A SECOND ARRANGEMENT, AND SUBJECTING SAID SECOND ARRANGEMENT TO SAID SECOND CONDITION, SAID ELEMENTS EACH COMPRISING AT LEAST ONE SEMICONDUCTOR RECTIFYING JUNCTION, SAID COORDINATE VALUES COMPRISING A ROW NUMBER AND COLUMN NUMBER, EACH ROW AND EACH COLUMN OF SAID JUNCTIONS COMPRISING RESPECTIVE ONES OF SAID COMBINATIONS, SAID RECTIFYING JUNCTIONS IN A SUBCOMBINATION BEING POLED IN THE SAME SENSE AND COMPRISING A SERIES COMBINATION, SAID FIRST AND SECOND CONDITIONS BEING THE APPLICATION OF FORWARD BIASING POTENTIALS AND REVERSE BIASING POTENTIALS RESPECTIVELY ACROSS JUNCTIONS IN A SUBCOMBINATION.