Serial adder and subtracter

Claim 1

A SERIAL DIGITAL COMPUTER COMPRISING A FULL ADDER HAVING TWO CODE INPUTS, A CARRY-INPUT, A SUM-OUTPUT AND A CARRY-OUTPUT, CODE-APPLYING MEANS FOR SERIALLY APPLYING A PLURALITY OF WORDS CONCURRENTLY TO EACH OF SAID INPUTS, EACH OF SAID WORDS HAVING A BINARY-CODED-DECIMAL NUMBER PART, SAID FULL ADDER INCLUDING FIRST MEANS FOR ADDING TOGETHER SAID NUMBER PARTS TO PRODUCE AN INITIAL SUM, ONE-CYCLE DELAY MEANS, MEANS CONNECTING SAID ONE-CYCLE DELAY MEANS BETWEEN SAID CARRY-OUTPUT AND SAID CARRYINPUT OF SAID FULL ADDER, SAID FULL ADDER INCLUDING ADDITIONAL MEANS FOR PERFORMING AN ADDITION OPERATION ON SAID INITIAL SUM AND ON SAID CARRY-INPUT TO PRODUCE AT SAID SUM-OUTPUT A FIRST BINARY-CODED-DECIMAL SUM, MULTIPLE DELAY MEANS PROVIDING A SERIAL DELAY TO EACH OF THE BITS APPLIED THERETO OF A TIME DURATION AT LEAST EQUAL TO THE TIME DURATION OF THE NUMBER PART OF SAID WORDS, MEANS CONNECTING SAID MULTIPLE DELAY MEANS BETWEEN SAID SUM-OUTPUT AND ONE OF SAID CODE-INPUTS, A CORRECTION SYSTEM CONNECTED TO SAID SUM-OUTPUT FOR PRODUCING A BINARY-CODED-DECIMAL NUMBER REPRESENTING THE DECIMAL-SIX WHEN SAID FIRST BINARY-CODED-DECIMAL SUM HAS A DECIMAL EQUIVALENT GREATER THAN NINE AND FOR PRODUCING A BINARY-CODED DECIMAL NUMBER REPRESENTING THE DECIMAL ZERO WHEN SAID FIRST BINARY-CODED-DECIMAL SUM HAS A DECIMAL EQUIVALENT OF NINE OR LESS, AND MEANS FOR APPLYING THE OUTPUT OF SAID CORRECTION SYSTEM TO THE OTHER OF SAID CODE INPUTS OF SAID FULL ADDER IN TIME SEQUENCE WITH SAID RESUBMITTED BINARY-CODED-DECIMAL SUM.