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US3082380A Expired / Lapsed US ⏱️ 0.0 years remaining

Transistor amplifier stage with high input impedance

Assignee: Sonotone Corp
•
Filing: 1961-07-13
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Granted: 1963-03-19
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Expires: 1981-07-13
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Abstract

No abstract record available.

Inventors

  • 👤 Frank A Herrmann

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 20:16
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/56; H03F1/565

Claims Analysis

Total Claims: 1
Claim 1
Independent Claim 296 words
IN A TRANSISTOR AMPLIFIER SYSTEM FOR AMPLIFYING AN INPUT SIGNAL FROM A HIGH-IMPEDANCE SIGNAL DEVICE, SUCH AS A PIEZOELECTRIC CERAMIC MICROPHONE, A FIRST, A SECOND AND A THIRD JUNCTION TRANSISTOR, EACH OF SAID THREE TRANSISTORS HAVING A BASE, AND TWO ADDITIONAL UNLIKE ELECTRODES CONSISTING OF EMITTER AND COLLECTOR, EACH OF SAID TRANSISTORS BEING OF THE SAME CONDUCTIVITY TYPE, A DIRECT-CURRENT SUPPLY SOURCE AND TWO-OPPOSITE POLARITY SUPPLY LEADS EXTENDING FROM THE OPPOSITE POLES OF SAID SOURCE AND CONNECTED RESPECTIVELY THROUGH DIRECT-CURRENT CIRCUITS TO THE COLLECTOR AND EMITTER OF SAID THIRD TRANSISTOR, A DIRECT-CURRENT SERIESCIRCUIT INCLUDING SERIALLY THE COLLECTOR AND EMITTER OF SAID SAID FIRST TRANSISTOR AND THE COLLECTOR OF SAID SECOND TRANSISTOR HAVING A COMMON DIRECT-CURRENT CONNECTION TO THE BASE OF SAID THIRD TRANSISTOR, AN INPUT CIRCUIT FROM SAID SIGNAL DEVICE HAVING ONE INPUT LEAD CONNECTED TO THE BASE OF SAID FIRST TRANSISTOR AND AN OPPOSITE POLARITY OTHER INPUT LEAD CONNECTED TO THE EMITTER OF SAID SECOND TRANSISTOR AND THE SUPPLY LEAD CONNECTED TO THE EMITTER OF SAID SECOND TRANSISTOR FOR IMPRESSING THE INPUT SIGNALS OF SAID DEVICE ON THE HIGH-IMPEDANCE CIRCUIT SERIALLY INCLUDING THE BASE AND EMITTER OF SAID FIRST TRANSISTOR AND THE COLLECTOR AND EMITTER OF SAID SECOND TRANSISTOR, AN EMITTER RESISTANCE CONNECTED BETWEEN THE EMITTER OF SAID THIRD TRANSISTOR AND THE SUPPLY LEAD CONNECTED TO THE EMITTER OF SAID SECOND TRANSISTOR, A DIRECT-CURRENT BIAS CIRCUIT INCLUDING BIAS RESISTANCE ELEMENTS CONNECTED PARALLEL TO SAID EMITTER RESISTANCE, AND A DIRECT-CURRENT BIAS CONNECTION FROM A SELECTED PORTION OF SAID BIAS RESISTANCE ELEMENTS TO THE BASE OF SAID SECOND TRANSISTOR FOR MAINTAINING A PREDETERMINED RELATION BETWEEN THE EMITTER DIRECT CURRENTS OF SAID FIRST AND SECOND TRANSISTORS AND APPLYING THROUGH SAID COMMON CONNECTION A CORRESPONDING DIRECT-CURRENT BIAS TO THE BASE OF SAID THIRD TRANSISTOR UNDER VARIATIONS OF AMBIENT TEMPERATURE.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1966-03-18 1966-09-17 1967-03-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1970-03-18 1970-09-17 1971-03-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1974-03-18 1974-09-17 1975-03-19 $7700.00 Window Closed / Lapsed

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