Capacitive type circulating register

Claim 1

A CIRCULATING REGISTER INCLUDING A PLURALITY OF STAGES COMPRISING IN EACH OF SAID STAGES A FIRST TRANSISTOR HAVING A BASE, EMITTER AND COLLECTOR, THE COLLECTOR OF SAID FIRST TRANSISTOR BEING ELECTRICALLY CONNECTED TO BOTH A FIRST CLOCK SOURCE AND TO A FIRST SIDE OF A FIRST CAPACITOR, THE SECOND SIDE OF SAID FIRST CAPACITOR AND THE EMITTER OF SAID FIRST TRANSISTOR BEING ELECTRICALLY CONNECTED TO GROUND, A SECOND TRANSISTOR HAVING AN EMITTER, BASE AND COLLECTOR, THE BASE OF SAID SECOND TRANSISTOR BEING ELECTRICALLY CONNECTED TO THE FIRST SIDE OF SAID FIRST CAPACITOR, MEANS FOR BIASING SAID FIRST AND SECOND TRANSISTORS TO CONDUCTION IN THE ABSENCE OF AN INPUT SIGNAL TO SAID STAGE, A SECOND CAPACITOR HAVING FIRST AND SECOND SIDES, THE SECOND SIDE OF SAID SECOND CAPACITOR AND EMITTER OF SAID SECOND TRANSISTOR BEING BOTH ELECTRICALLY CONNECTED TO GROUND, THE COLLECTOR OF SAID SECOND TRANSISTOR BEING CONNECTED TO A SECOND CLOCK MEANS, THE COLLECTOR OF SAID SECOND TRANSISTOR BEING ALSO CONNECTED TO SAID FIRST SIDE OF SAID SECOND CAPACITOR, THIRD CLOCK MEANS ELECTRICALLY CONNECTED TO SAID FIRST SIDE OF SAID FIRST CAPACITOR, AND FOURTH CLOCK MEANS ELECTRICALLY CONNECTED TO SAID FIRST SIDE OF SAID SECOND CAPACITOR.