Potential testing circuits

Claim 1

A POTENTIAL TESTING CIRCUIT RESPONSIVE TO A TEST POINT POTENTIAL WITHIN A CERTAIN RANGE OF VALUES, COMPRISING FIRST AND SECOND TRANSISTORS, A COMMON EMITTER RESISTANCE FOR SAID TRANSISTORS, A COLLECTOR RESISTANCE FOR AT LEAST SAID FIRST TRANSISTOR, A COLLECTOR-TO-BASE CONNECTION FROM SAID FIRST TRANSISTOR TO THE SECOND TRANSISTOR, SAID TRANSISTORS AND RESISTANCES TOGETHER FORMING A TRIGGER CIRCUIT HAVING AN UNTRIGGERED STATE IN WHICH ONE OF THE TRANSISTORS IS RELATIVELY HEAVILY CONDUCTIVE COMPARED WITH THE OTHER TRANSISTOR AND A TRIGGERED STATE IN WHICH THIS LATTER TRANSISTOR IS THE MORE HEAVILY CONDUCTIVE BUT PRODUCES ACROSS THE COMMON EMITTER RESISTANCE A LESSER POTENTIAL DIFFERENCE THAN IS PRODUCED ACROSS IT IN THE UNTRIGGERED STATE, A BASE CONNECTION FROM THE FRIST TRANSISTOR TO THE TEST POINT WHEREBY THE TRIGGER CIRCUIT WILL BE TRIGGERED FROM ITS UNTRIGGERED STATE IN RESPONSE TO A TEST POINT POTENTIAL WITHIN SAID RANGE OF VALUES, AND A HIGH-SPEED RELAY CONNECTED TO BE OPERATED IN ONE STATE OF THE TRIGGER CIRCUIT, THE LESSER POTENTIAL DIFFERENCE PRODUCED ACROSS THE COMMON EMITTER RESISTANCE IN THE TRIGGERED STATE OF THE TRIGGER CIRCUIT ACTING THROUGH THE EMITTER-BASE DIODE OF THE FIRST TRANSISTOR TO HOLD THE TEST POINT AT A POTENTIAL OUTSIDE SAID RANGE OF VALUES.