Electronic stepping integrator circuit

Claim 1

AN ELECTRONIC STEPPING INTEGRATOR CIRCUIT FOR PRODUCING AN OUTPUT SIGNAL AT A PAIR OF OUTPUT TERMINALS THAT IS PROPORTIONAL TO THE INTEGRAL OF THE INPUT SIGNAL APPLIED TO A PAIR OF INPUT TERMINALS IN RESPONSE TO FIRST AND SECOND FIXED VOLTAGES AND FIRST, SECOND AND THIRD SIGNALS PERIODICALLY VARYING BETWEEN FIRST AND SECOND VOLTAGE LEVELS, SAID CIRCUIT COMPRISING: FIRST AND SECOND JUNCTIONS; FIRST, SECOND AND THIRD DIODES, EACH HAVING FIRST AND SECOND ELECTRODES, CONNECTED IN SERIES BETWEEN SAID FIRST AND SECOND JUNCTIONS, THE FIRST ELECTRODES OF SAID FIRST AND THIRD DIODES BEING CONNECTED TO SAID FIRST AND SECOND JUNCTIONS, RESPECTIVELY, THE SECOND AND FIRST ELECTRODES OF SAID FIRST AND SECOND DIODES, RESPECTIVELY, BEING CONNECTED TO EACH OTHER, AND THE SECOND ELECTRODES OF SAID SECOND AND THIRD DIODES BEING CONNECTED TO EACH OTHER; FOURTH, FIFTH AND SIXTH DIODES, EACH HAVING FIRST AND SECOND ELECTRODES, CONNECTED IN SERIES BETWEEN SAID FIRST AND SECOND JUNCTIONS, THE FIRST ELECTRODES OF SAID FOURTH AND SIXTH DIODES BEING CONNECTED TO SAID FIRST AND SECOND JUNCTIONS, RESPECTIVELY, THE SECOND AND FIRST ELECTRODES OF SAID FOURTH AND FIFTH DIODES, RESPECTIVELY, BEING CONNECTED TO EACH OTHER, AND THE SECOND ELECTRODES OF SAID FIFTH AND SIXTH DIODES BEING CONNECTED TO EACH OTHER; SEVENTH, EIGHTH AND NINTH DIODES, EACH HAVING FIRST AND SECOND ELECTRODES, CONNECTED IN SERIES BETWEEN SAID FIRST AND SECOND JUNCTIONS, THE FIRST ELECTRODES OF SAID SEVENTH AND NINTH DIODES BEING CONNECTED TO SAID FIRST AND SECOND JUNCTIONS, RESPECTIVELY, THE SECOND AND FIRST ELECTRODES OF SAID SEVENTH AND EIGHTH DIODES, RESPECTIVELY, BEING CONNECTED TO EACH OTHER, AND THE SECOND ELECTRODES OF SAID EIGHTH AND NINTH DIODES BEING CONNECTED TO EACH OTHER; FIRST, SECOND AND THIRD MEANS FOR RECEIVING THE FIRST, SECOND AND THIRD SIGNALS, RESPECTIVELY; FIRST SECOND AND THIRD CAPACITORS CONNECTED BETWEEN SAID FIRST, SECOND AND THIRD MEANS AND THE SECOND ELECTRODE OF SAID FIRST, FOURTH AND SEVENTH DIODES, RESPECTIVELY; FIRST, SECOND AND THIRD RESISTORS CONNECTED BETWEEN SAID THIRD, FIRST AND SECOND MEANS AND THE SECOND ELECTRODE OF SAID THIRD, SIXTH AND NINTH DIODES, RESPECTIVELY; TENTH, ELEVENTH AND TWELFTH DIODES, EACH HAVING FIRST AND SECOND ELECTRODES, THE FIRST ELECTRODES OF SAID TENTH, ELEVENTH AND TWELFTH DIODES BEING CONNECTED TO THE FIRST ELECTRODES OF SAID SECOND, FIFTH AND EIGHTH DIODES, RESPECTIVELY, AND THE SECOND ELECTRODES OF SAID TENTH, ELEVENTH AND TWELFTH DIODES BEING CONNECTED TO SAID SECOND, THIRD AND FIRST MEANS, RESPECTIVELY; AN INPUT RESISTOR CONNECTED BETWEEN THE INPUT TERMINALS AND SAID FIRST JUNCTION; FOURTH AND FIFTH MEANS FOR RECEIVING THE FIRST AND SECOND FIXED VOLTAGES, RESPECTIVELY; AND AN OUTPUT LOAD RESISTOR CONNECTED BETWEEN SAID FOURTH MEANS AND SECOND JUNCTION, THE OUTPUT TERMINALS BEING CONNECTED BETWEEN SAID SECOND JUNCTION AND SAID FIFTH MEANS.