US3074639A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fast-operating adder circuits
Assignee: US Philips Corp
•
Filing: 1959-08-05
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Granted: 1963-01-22
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Expires: 1979-08-05
Abstract
No abstract record available.
Inventors
- 👤 Morgan Leonard Peter
- 👤 Weaver John Anthony
- 👤 Jarvis Denis Brian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:13
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/501; G06F7/502
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
167 words
A BINARY HALF-ADDER COMPRISING TWO INPUT TERMINALS AND TWO TRANSISTORS EACH HAVING A COLLECTOR, AN EMITTER AND A BASE, MEANS FOR APPLYING INPUT SIGNALS IN THE FORM OF CURRENT OR NO CURRENT TO THE INPUT TERMINALS, TWO OUTPUT TERMINALS WHICH DELIVER THE PARTIAL SUM AND THE PARTIAL CARRY RESPECTIVELY, LIKEWISE IN THE FORM OF CURRENT OR NO CURRENT, CHARACTERIZED IN THAT THE FIRST INPUT TERMINAL IS CONNECTED VIA A FIRST RESISTOR, WHICH MAY HAVE THE RESISTANCE 0, TO THE EMITTER OF THE FIRST TRANSISTOR AND IS ALSO CONNECTED, THROUGH A SUBSTANTIALLY IMPEDANCELESS CONNECTION, TO THE BASE OF THE SECOND TRANSISTOR; THAT THE SECOND INPUT TERMINAL IS CONNECTED VIA A SECOND RESISTOR TO THE EMITTER OF THE SECOND TRANSISTOR AND IS ALSO CONNECTED, THROUGH A SUBSTANTIALLY IMPEDANCELESS CONNECTION, TO THE BASE OF THE FIRST TRANSISTOR; THAT THE EMITTER OF THE FIRST TRANSISTOR IS CONNECTED VIA A THIRD RESISTOR TO AN ADDITIONAL TERMINAL AND THE EMITTER OF THE SECOND TRANSISTOR IS CONNECTED VIA A FOURTH RESISTOR TO AN ADDITIONAL
Claim 2
Dependent Claim
167 words
A BINARY HALF-ADDER COMPRISING TWO INPUT TERMINALS AND TWO TRANSISTORS EACH HAVING A COLLECTOR, AN EMITTER AND A BASE, MEANS FOR APPLYING INPUT SIGNALS IN THE FORM OF CURRENT OR NO CURRENT TO THE INPUT TERMINALS, TWO OUTPUT TERMINALS WHICH DELIVER THE PARTIAL SUM AND THE PARTIAL CARRY RESPECTIVELY, LIKEWISE IN THE FORM OF CURRENT OR NO CURRENT, CHARACTERIZED IN THAT THE FIRST INPUT TERMINAL IS CONNECTED VIA A FIRST RESISTOR, WHICH MAY HAVE THE RESISTANCE 0, TO THE EMITTER OF THE FIRST TRANSISTOR AND IS ALSO CONNECTED, THROUGH A SUBSTANTIALLY IMPEDANCELESS CONNECTION, TO THE BASE OF THE SECOND TRANSISTOR; THAT THE SECOND INPUT TERMINAL IS CONNECTED VIA A SECOND RESISTOR TO THE EMITTER OF THE SECOND TRANSISTOR AND IS ALSO CONNECTED, THROUGH A SUBSTANTIALLY IMPEDANCELESS CONNECTION, TO THE BASE OF THE FIRST TRANSISTOR; THAT THE EMITTER OF THE FIRST TRANSISTOR IS CONNECTED VIA A THIRD RESISTOR TO AN ADDITIONAL TERMINAL AND THE EMITTER OF THE SECOND TRANSISTOR IS CONNECTED VIA A FOURTH RESISTOR TO AN ADDITIONAL
References Cited (Backward Citations)
US2995666A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1966-01-21 | 1966-07-23 | 1967-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1970-01-21 | 1970-07-23 | 1971-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1974-01-21 | 1974-07-23 | 1975-01-22 | $7700.00 | Window Closed / Lapsed |