Combined limiter and threshold circuit

Claim 1

A SIGNAL LIMITER AND THRESHOLD CIRCUIT COMPRISING FIRST AND SECOND TRANSISTORS, EACH TRANSISTOR HAVING AN EMITTER, A BASE AND A COLLECTOR, A SOURCE OF SUPPLY POTENTIAL HAVING FIRST AND SECOND TERMINALS OF DIFFERENT POTENTIAL, A FIRST RESISTOR CONNECTED AT ONE END TO THE EMITTERS OF SAID FIRST AND SECOND TRANSISTORS AND AT THE OTHER END TO SAID FIRST TERMINAL OF SAID SOURCE OF SUPPLY POTENTIAL, A SECOND RESISTOR CONNECTED BETWEEN THE COLLECTOR OF SAID FIRST TRANSISTOR AND SAID SECOND TERMINAL OF SAID SUPPLY SOURCE, A THIRD RESISTOR CONNECTED BETWEEN SAID COLLECTOR OF SAID SECOND TRANSISTOR AND SAID SECOND TERMINAL OF SAID SUPPLY SOURCE, SAID BASE OF SAID SECOND TRANSISTOR BEING DIRECTLY CONNECTED TO SAID COLLECTOR OF SAID FIRST TRANSISTOR, SAID FIRST RESISTOR HAVING A RESISTANCE AT LEAST EQUAL TO THE VALUE WHICH WILL CAUSE SAID CIRCUIT TO HAVE A HYSTERESIS LOOP TYPE INPUT-OUTPUT CHARACTERISTIC, SAID BASE OF SAID FIRST TRANSISTOR BEING ELECTRICALLY ISOLATED FROM SAID BASE, COLLECTOR AND EMITTER OF SAID SECOND TRANSISTOR, WHEREBY THE SIGNAL SUPPLIED TO THE BASE OF SAID FIRST TRANSISTOR IS INDEPENDENT OF THE STATE OF CONDUCTION OF SAID SECOND TRANSISTOR, MEANS FOR BIASING SAID BASE OF SAID FIRST TRANSISTOR TO A SELECTED POINT ON THE BI-VALUED PORTION OF SAID HYSTERESIS LOOP CHARACTERISTIC, AND MEANS FOR SUPPLYING AN INPUT SIGNAL TO SAID BASE OF SAID FIRST TRANSISTOR.