US3013955A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of transistor manufacture
Assignee: Fairchild Semiconductor Corp
•
Filing: 1959-04-29
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Granted: 1961-12-19
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Expires: 1979-04-29
Abstract
No abstract record available.
Inventors
- 👤 Roberts Cornelius Sheldon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 02:33
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/40; H10P14/46; H10P95/00; Y; Y10; Y10S; Y10S148/00; Y10S148/062
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
140 words
A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF DIFFUSING SELECTED IMPURITIES INTO SEMICONDUCTING MATERIAL TO FORM LAYERS OF ZONES OF OPPOSITE TYPE SEMICONDUCTING MATERIAL SEPARATED BY RECTIFYING JUNCTIONS, AT LEAST TWO OF SAID ZONES EXTENDING TO ONE FACE OF THE DEVICE, CHEMICALLY PLATING GOLD UPON THE N MATERIAL IN THE PRESENCE OF INTENSE LIGHT FORMING A PHOTOVOLTAGE MAINTAINING THE N MATERIAL CATHODIC, WHEREBY SAID GOLD PLATES ALL OF THE SURFACE OF SAID N-TYPE MATERIAL TO AND NOT INCLUDING SAID JUNCTION, ELECTROPLATING GOLD UPON THE P MATERIAL BY MAINTAINING SAME ELECTRICALLY NEGATIVE WITH RESPECT TO A GOLD ANODE IN AN ELECTROPLATING BATH, WHEREBY THE ENTIRE SURFACE OF P-TYPE MATERIAL IS PLATED TO AND NOT INCLUDING SAID JUNCTION, AND ALLOYING THE GOLD PLATING INTO SAID SURFACES AT A TEMPERATURE ABOVE THE EUTECTIC TEMPERATURE OF GOLD AND TRANSISTOR MATERIAL TO
Claim 2
Independent Claim
140 words
A METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE COMPRISING THE STEPS OF DIFFUSING SELECTED IMPURITIES INTO SEMICONDUCTING MATERIAL TO FORM LAYERS OF ZONES OF OPPOSITE TYPE SEMICONDUCTING MATERIAL SEPARATED BY RECTIFYING JUNCTIONS, AT LEAST TWO OF SAID ZONES EXTENDING TO ONE FACE OF THE DEVICE, CHEMICALLY PLATING GOLD UPON THE N MATERIAL IN THE PRESENCE OF INTENSE LIGHT FORMING A PHOTOVOLTAGE MAINTAINING THE N MATERIAL CATHODIC, WHEREBY SAID GOLD PLATES ALL OF THE SURFACE OF SAID N-TYPE MATERIAL TO AND NOT INCLUDING SAID JUNCTION, ELECTROPLATING GOLD UPON THE P MATERIAL BY MAINTAINING SAME ELECTRICALLY NEGATIVE WITH RESPECT TO A GOLD ANODE IN AN ELECTROPLATING BATH, WHEREBY THE ENTIRE SURFACE OF P-TYPE MATERIAL IS PLATED TO AND NOT INCLUDING SAID JUNCTION, AND ALLOYING THE GOLD PLATING INTO SAID SURFACES AT A TEMPERATURE ABOVE THE EUTECTIC TEMPERATURE OF GOLD AND TRANSISTOR MATERIAL TO
References Cited (Backward Citations)
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Cited
US2694040A
Cited
US2873303A
Cited
US2814589A
Cited
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Cited
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Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1964-12-18 | 1965-06-19 | 1965-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1968-12-18 | 1969-06-19 | 1969-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1972-12-18 | 1973-06-19 | 1973-12-19 | $7700.00 | Window Closed / Lapsed |