US2887415A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making alloyed junction in a silicon wafer
Assignee: Honeywell Inc
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Filing: 1955-05-12
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Granted: 1959-05-19
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Expires: 1975-05-12
Abstract
No abstract record available.
Inventors
- 👤 Stevenson Alden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 04:19
CPC Classifications
H; H10; H10P; H10P95/00; C; C30; C30B; C30B13/00; C30B31/00; C30B31/04; H10D; H10D99/00
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
143 words
THE METHOD OF FORMING AN ALLOYED JUNCTION AREA IN A WAFER OF SINGLE-CRYSTALLINE SILICON SEMICONDUCTOR MATERIAL OF N-TYPE CONDUCTIVITY WHICH INCLUDES PLACING AN ELONGATED IMPURITY SOURCE BODY SELECTED FROM THE CLASS CONSISTING OF ALUMIMUM, GOLD-GALLIUM ALLOY AND GOLD-INDIUM ALLOY AND HAVING A SUBSTANTIALLY CIRCULAR CROSS-SECTION ADJACENT TO AND IN CONTACT WITH A SURFACE OF SAID WAFER, THE ELONGATED AXIS OF SAID IMPURITY SOURCE BODY BEING ARRANGED PARALLEL TO SAID CONTACTING SURFACE, PASSING SAID WAFER AND IMPURITY SOURCE COMBINATION THROUGH A HEATING ZONE WHEREIN THE TEMPERATURE IS ELEVATED TO A TEMPERATURE EXCEEDING THE FUSION POINT OF SAID IMPURITY SOURCE BODY, AND THEN URGING SAID IMPURITY SOURCE BODY AGAINST SAID SEMICONDUCTOR BODY AS FUSION PROCEEDS, THEREBY INCREASING THE AREA OF CONTACT BETWEEN SAID WAFER AND SAID IMPURITY SOURCE, AND MAINTAINING SAID ELEVATED TEMPERATURE UNTIL ALLOYING IS ACHIEVED BETWEEN SAID IMPURITY SOURCE AND SAID SEMICONDUCTOR MATERIAL.
Claim 2
Independent Claim
143 words
THE METHOD OF FORMING AN ALLOYED JUNCTION AREA IN A WAFER OF SINGLE-CRYSTALLINE SILICON SEMICONDUCTOR MATERIAL OF N-TYPE CONDUCTIVITY WHICH INCLUDES PLACING AN ELONGATED IMPURITY SOURCE BODY SELECTED FROM THE CLASS CONSISTING OF ALUMIMUM, GOLD-GALLIUM ALLOY AND GOLD-INDIUM ALLOY AND HAVING A SUBSTANTIALLY CIRCULAR CROSS-SECTION ADJACENT TO AND IN CONTACT WITH A SURFACE OF SAID WAFER, THE ELONGATED AXIS OF SAID IMPURITY SOURCE BODY BEING ARRANGED PARALLEL TO SAID CONTACTING SURFACE, PASSING SAID WAFER AND IMPURITY SOURCE COMBINATION THROUGH A HEATING ZONE WHEREIN THE TEMPERATURE IS ELEVATED TO A TEMPERATURE EXCEEDING THE FUSION POINT OF SAID IMPURITY SOURCE BODY, AND THEN URGING SAID IMPURITY SOURCE BODY AGAINST SAID SEMICONDUCTOR BODY AS FUSION PROCEEDS, THEREBY INCREASING THE AREA OF CONTACT BETWEEN SAID WAFER AND SAID IMPURITY SOURCE, AND MAINTAINING SAID ELEVATED TEMPERATURE UNTIL ALLOYING IS ACHIEVED BETWEEN SAID IMPURITY SOURCE AND SAID SEMICONDUCTOR MATERIAL.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1962-05-18 | 1962-11-17 | 1963-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1966-05-18 | 1966-11-17 | 1967-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1970-05-18 | 1970-11-17 | 1971-05-19 | $7700.00 | Window Closed / Lapsed |