US20030198097A1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device having preamplifier with improved data propagation speed
Assignee: Renesas Technology Corp
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Filing: 2002-10-16
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Granted: —
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Expires: 2022-10-16
Abstract
Abstract A preamplifier includes an amplifier circuit amplifying a signal level of read data, a latency shifter outputting the read data onto a data line pair in response to an internal signal determining a timing of outputting the read data onto the data bus pair, and a driver outputting the read data onto the data bus pair. The amplifier circuit receives the internal signal and outputs the read data onto the data line pair while bypassing the latency shifter when the internal signal is already at high level at the timing when the signal level of the read data is amplified. As a result, a semiconductor memory device can speed up propagation of the read data from the preamplifier onto the data bus pair in a high frequency operation.
Inventors
- 👤 Takashi Kono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:33
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/1069; G11C2207/00; G11C2207/10; G11C2207/107
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
190 words
1 . A semiconductor memory device allowing data input/output in synchronization with a rise and a fall of an external clock, comprising: a memory cell array storing data; a control circuit producing first and second signals based on an adjacent clock cycle as a starting point; a preamplifier amplifying read data read from said memory cell array to be output onto a data bus based on said first and second signals; and a data output circuit externally outputting said read data output onto said data bus, wherein said preamplifier amplifies a signal level of said read data based on said first signal and outputs said read data having the amplified signal level onto said data bus based on said second signal when a timing of receiving said second signal is later than a timing of receiving said first signal, and amplifies a signal level of said read data based on said first signal and outputs said read data having the amplified signal level onto said data bus based on the first signal when a timing of receiving said second signal is earlier than a timing of receiving said first signal.
Claim 2
Dependent Claim
190 words
1 . A semiconductor memory device allowing data input/output in synchronization with a rise and a fall of an external clock, comprising: a memory cell array storing data; a control circuit producing first and second signals based on an adjacent clock cycle as a starting point; a preamplifier amplifying read data read from said memory cell array to be output onto a data bus based on said first and second signals; and a data output circuit externally outputting said read data output onto said data bus, wherein said preamplifier amplifies a signal level of said read data based on said first signal and outputs said read data having the amplified signal level onto said data bus based on said second signal when a timing of receiving said second signal is later than a timing of receiving said first signal, and amplifies a signal level of said read data based on said first signal and outputs said read data having the amplified signal level onto said data bus based on the first signal when a timing of receiving said second signal is earlier than a timing of receiving said first signal.
Claim 3
Dependent Claim
180 words
2 . The semiconductor memory device according to claim 1 , wherein said preamplifier includes an amplifier circuit receiving said first and second signals to amplify a signal level of said read data based on said first signal, a data shift circuit receiving said second signal to shift said read data having the signal level amplified by said amplifier circuit, based on said second signal, a driver outputting said read data onto said data bus, when a timing of receiving said second signal is later than a timing of receiving said first signal in said amplifier circuit, said amplifier circuit outputs said read data having the amplified signal level to said data shift circuit based on said first signal and said data shift circuit outputs said read data shifted based on said second signal to said driver, and when a timing of receiving said second signal is earlier than a timing of receiving said first signal in said amplifier circuit, said amplifier circuit outputs said read data having the amplified signal level to said driver based on said first signal.
Claim 4
Dependent Claim
178 words
3 . The semiconductor memory device according to claim 2 , wherein said preamplifier further includes a first data line connecting an input node of said data shift circuit to a first output node of said amplifier circuit and a second data line connecting an input node of said driver to an output node of said data shift circuit and to a second output node of said amplifier circuit, when a timing of receiving said second signal is later than a timing of receiving said first signal in said amplifier circuit, said amplifier circuit outputs said read data having the amplified signal level onto said first data line based on said first signal and said data shift circuit outputs said read data shifted based on said second signal onto said second data line, and when a timing of receiving said second signal is earlier than a timing of receiving said first signal in said amplifier circuit, said amplifier circuit outputs said read data having the amplified signal level onto said second data line based on said first signal.
Claim 5
Dependent Claim
90 words
4 . The semiconductor memory device according to claim 2 , wherein said amplifier circuit further outputs said read data having the amplified signal level to said driver based on said second signal when a timing of receiving said second signal is later than a timing of receiving said first signal, and further outputs said read data having the amplified signal level to said data shift circuit based on said first signal when a timing of receiving said second signal is earlier than a timing of receiving said first signal.
Claim 6
Dependent Claim
200 words
5 . The semiconductor memory device according to claim 4 , wherein said preamplifier further includes a first data line connecting an input node of said data shift circuit to a first output node of said amplifier circuit, and a second data line connecting an input node of said driver to an output node of said data shift circuit and to a second output node of said amplifier circuit, when a timing of receiving said second signal is later than a timing of receiving said first signal in said amplifier circuit, said amplifier circuit outputs said read data having the amplified signal level onto said first data line based on said first signal and outputs said read data having the amplified signal level onto said second data line based on said second signal and said data shift circuit outputs said read data shifted based on said second signal onto said second data line, and when a timing of receiving said second signal is earlier than a timing of receiving said first signal in said amplifier circuit, said amplifier circuit outputs said read data having the amplified signal level onto said first and second data lines based on said first signal.
Claim 7
Dependent Claim
91 words
6 . The semiconductor memory device according to claim 5 , wherein said amplifier circuit includes a differential amplifier taking in and amplifying said read data based on said first signal, a first output circuit latching the read data having the signal level amplified by said differential amplifier and outputting the read data onto said first data line, and a second output circuit outputting the read data having the signal level amplified by said differential amplifier based on said first signal onto said second data line when receiving said second signal.
Claim 8
Dependent Claim
50 words
7 . The semiconductor memory device according to claim 6 , wherein said amplifier circuit further includes a signal producing circuit producing a third signal when receiving both said first and second signals, and said second output circuit is activated by said third signal produced by said signal producing circuit.
References Cited (Backward Citations)
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