US20030157748A1 — Process of vertically stacking multiple wafers su…

Claim 1

Independent Claim 71 words

1 . A method of vertically stacking wafers, comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via respective metallic lines on opposing surfaces of the adjacent wafers, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect.

Claim 2

Dependent Claim 71 words

1 . A method of vertically stacking wafers, comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via respective metallic lines on opposing surfaces of the adjacent wafers, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect.

Claim 3

Dependent Claim 72 words

2 . The method as claimed in claim 1 , wherein each via is formed by: selectively etching the top wafer to form a via; depositing an oxide layer to insulate a sidewall of the via; forming a barrier/seed layer in the via; and depositing a conduction metal on the barrier/seed layer in the via for providing an electrical connection between active devices on the vertically stacked wafers and the external interconnect.

Claim 4

Dependent Claim 32 words

3 . The method as claimed in claim 1 , wherein the metallic lines are Copper (Cu) lines deposited to serve as electrical contacts between active devices on the vertically stacked wafers.

Claim 5

Dependent Claim 25 words

4 . The method as claimed in claim 2 , wherein the conduction metal deposited in the via is copper (Cu) or a Cu alloy.

Claim 6

Dependent Claim 36 words

5 . The method as claimed in claim 2 , wherein the barrier/seed layer contains a barrier layer deposited in the via, and a copper (Cu) seed layer deposited in the trench overlying the barrier layer.

Claim 7

Dependent Claim 61 words

6 . The method as claimed in claim 5 , wherein the barrier layer is comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and the Cu seed layer is comprised of a thin layer of copper (Cu) deposited on the barrier layer by chemical vapor deposition (CVD) process.

Claim 8

Dependent Claim 51 words

7 . The method as claimed in claim 1 , further comprising dummy vias arranged on opposing surfaces of the adjacent wafers to increase the surface area for wafer-to-wafer bonding and serve as auxiliary structures such as ground planes or heat conduits for the active devices on the vertically stacked wafers.

Claim 9

Dependent Claim 37 words

8 . The method as claimed in claim 1 , wherein the vias are formed tapered from the top to the bottom via trench to increase the surface area for wafer to-wafer bonding in the adjacent wafers.

Claim 10

Dependent Claim 117 words

9 . The method as claimed in claim 1 , wherein each via is formed by a dual damascene process comprised of: selectively etching the top wafer to form an upper trench section of a via; depositing an oxide layer to insulate a sidewall of the upper trench section of the via; selectively etching the oxide layer in the upper trench section of the via to form a lower trench section of the via; depositing a barrier/seed layer in the upper trench section and the lower trench section of the via; and depositing a conduction metal on the barrier/seed layer for providing an electrical connection between active devices on the vertically stacked wafers and an external interconnect.

Claim 11

Dependent Claim 97 words

10 . The method as claimed in claim 9 , wherein the barrier/seed layer includes a barrier layer comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and deposited in the upper trench section overlying the oxide layer and the lower trench section of the via; and a copper (Cu) seed layer comprised of a thin layer of copper (Cu) deposited on the barrier layer, and deposited overlying the barrier layer in both the upper trench section and the lower trench section of the via.

Claim 12

Dependent Claim 45 words

11 . The method as claimed in claim 1 , wherein the vias are formed during a Shallow Trench Isolation (STI) process in the top wafer before the adjacent wafers are bonded, via the respective metallic lines deposited on opposing surfaces of the adjacent wafers.

Claim 13

Dependent Claim 127 words

12 . A method of forming vertically stacked wafers, comprising: depositing a plurality of metallic lines on opposing surfaces of top and bottom wafers; forming a conductive plug; bonding the adjacent wafers, via respective metallic lines, to form vertically stacked wafers; and forming at least one via on the top wafer to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect, by selectively etching through the top wafer until stopped by the conductive plug, depositing an oxide layer to insulate a sidewall of the via, depositing a barrier/seed layer on the bottom of the via, and filling the via with a conduction metal to serve as electrical connections between active devices on the vertically stacked wafers and the external interconnect.

Claim 14

Dependent Claim 127 words

12 . A method of forming vertically stacked wafers, comprising: depositing a plurality of metallic lines on opposing surfaces of top and bottom wafers; forming a conductive plug; bonding the adjacent wafers, via respective metallic lines, to form vertically stacked wafers; and forming at least one via on the top wafer to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect, by selectively etching through the top wafer until stopped by the conductive plug, depositing an oxide layer to insulate a sidewall of the via, depositing a barrier/seed layer on the bottom of the via, and filling the via with a conduction metal to serve as electrical connections between active devices on the vertically stacked wafers and the external interconnect.

Claim 15

Dependent Claim 32 words

13 . The method as claimed in claim 12 , wherein the metallic lines are Copper (Cu) lines deposited to serve as electrical contacts between active devices on the vertically stacked wafers.

Claim 16

Dependent Claim 25 words

14 . The method as claimed in claim 12 , wherein the conduction metal deposited in the via is copper (Cu) or a Cu alloy.

Claim 17

Dependent Claim 36 words

15 . The method as claimed in claim 12 , wherein the barrier/seed layer contains a barrier layer deposited in the via, and a copper (Cu) seed layer deposited in the via overlying the barrier layer.

Claim 18

Dependent Claim 56 words

16 . The method as claimed in claim 15 , wherein the barrier layer is comprised of a material selected from one of the group including tantalum, titanium, and tungsten, and the Cu seed layer is comprised of a few layers of copper (Cu) atoms deposited on the barrier layer by chemical vapor deposition (CVD) process.

Claim 19

Dependent Claim 51 words

17 . The method as claimed in claim 12 , further comprising dummy vias arranged on opposing surfaces of the adjacent wafers to increase the surface area for wafer-to-wafer bonding and serve as auxiliary structures such as ground planes or heat conduits for the active devices on the vertically stacked wafers.

Claim 20

Dependent Claim 37 words

18 . The method as claimed in claim 12 , wherein the via is formed tapered from the top to the bottom via trench to increase the surface area for wafer to-wafer bonding in the adjacent wafers.

Claim 21

Dependent Claim 124 words

19 . A three-dimensional (3-D) vertically stacked wafer system, comprising: a first wafer including an active region to support one or more integrated circuit (IC) devices; a second wafer including an active region to support one or more integrated circuit (IC) devices; metallic lines deposited on opposing surfaces of the first and second wafers at designated areas to establish metal bonding between the first and second wafers in a stack and provide electrical connections between active IC devices on the first and second wafers in the stack; and one or more vias formed, via the active region of the first wafer, to serve as electrical connections between the active IC devices on the first and second wafers in the stack and an external interconnect.

Claim 22

Dependent Claim 124 words

19 . A three-dimensional (3-D) vertically stacked wafer system, comprising: a first wafer including an active region to support one or more integrated circuit (IC) devices; a second wafer including an active region to support one or more integrated circuit (IC) devices; metallic lines deposited on opposing surfaces of the first and second wafers at designated areas to establish metal bonding between the first and second wafers in a stack and provide electrical connections between active IC devices on the first and second wafers in the stack; and one or more vias formed, via the active region of the first wafer, to serve as electrical connections between the active IC devices on the first and second wafers in the stack and an external interconnect.

Claim 23

Dependent Claim 48 words

20 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 19 , wherein the metallic lines include Copper (Cu) lines deposited on opposing surfaces of the first and second wafers to serve as electrical contacts between active IC devices on the first and second wafers.

Claim 24

Dependent Claim 78 words

21 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 20 , wherein each via is formed by: selectively etching the first wafer to form a via; depositing an oxide layer to insulate a sidewall of the via; forming a barrier/seed layer in the via; and depositing a conduction metal on the barrier/seed layer in the via for providing an electrical connection between active IC devices on the vertically stacked wafers and the external interconnect.

Claim 25

Dependent Claim 60 words

22 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 21 , wherein the conduction metal deposited in the via is copper (Cu) or a Cu alloy, and the barrier/seed layer includes a barrier layer deposited in the via overlying the oxide layer and a copper (Cu) seed layer deposited in the via overlying the barrier layer.

Claim 26

Dependent Claim 66 words

23 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 22 , wherein the barrier layer is comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and the Cu seed layer is comprised of a thin layer of copper (Cu) deposited on the barrier layer by chemical vapor deposition (CVD) process.

Claim 27

Dependent Claim 118 words

24 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 20 , wherein each via is formed by a dual damascene process comprised of: selectively etching the top wafer to form an upper trench section of the via; depositing an oxide layer to insulate a sidewall of the upper trench section of the via; etching the oxide layer in the upper trench section to form a lower trench section of the via; depositing a barrier/seed layer in the upper trench section and the lower trench section of the via; and depositing a conduction metal on the barrier/seed layer for providing an electrical connection between active devices on the vertically stacked wafers and the external interconnect.

Claim 28

Dependent Claim 102 words

25 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 24 , wherein the barrier/seed layer includes a barrier layer comprised of a material selected from one of the group including tantalum (Ta), tantalum nitride (TaN), titanium (Ti), and tungsten (W), and deposited in the upper trench section overlying the oxide layer and the lower trench section of the via; and a copper (Cu) seed layer comprised of a thin layer of copper (Cu) deposited on the barrier layer, and deposited overlying the barrier layer in both the upper trench section and the lower trench section of the via.

Claim 29

Dependent Claim 54 words

26 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 20 , wherein the vias are formed during a Shallow Trench Isolation (STI) process in the first wafer before the first and second wafers are bonded, via the respective metallic lines deposited on opposing surfaces of the first and second wafers.

Claim 30

Dependent Claim 144 words

27 . A three-dimensional (3-D) vertically stacked wafer system, comprising: a first stack of wafers in which adjacent wafers are bonded, via metallic lines deposited on opposing surfaces of the adjacent wafers at designated areas to establish metal bonding between the adjacent wafers and provide electrical connections between active IC devices on the adjacent wafers; a first stack of wafers in which adjacent wafers are bonded, via metallic lines deposited on opposing surfaces of the adjacent wafers at designated areas to establish metal bonding between the adjacent wafers and provide electrical connections between active IC devices on the adjacent wafers; and one or more vias formed on opposing surfaces of the first stack of wafers and the second stack of adjacent wafers to serve as electrical connections between the active IC devices on the first and second stacks of wafers and an external interconnect.

Claim 31

Dependent Claim 144 words

27 . A three-dimensional (3-D) vertically stacked wafer system, comprising: a first stack of wafers in which adjacent wafers are bonded, via metallic lines deposited on opposing surfaces of the adjacent wafers at designated areas to establish metal bonding between the adjacent wafers and provide electrical connections between active IC devices on the adjacent wafers; a first stack of wafers in which adjacent wafers are bonded, via metallic lines deposited on opposing surfaces of the adjacent wafers at designated areas to establish metal bonding between the adjacent wafers and provide electrical connections between active IC devices on the adjacent wafers; and one or more vias formed on opposing surfaces of the first stack of wafers and the second stack of adjacent wafers to serve as electrical connections between the active IC devices on the first and second stacks of wafers and an external interconnect.

Claim 32

Dependent Claim 56 words

28 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 27 , wherein the metalic lines include Copper (Cu) lines deposited on opposing surfaces of the adjacent wafers in the first and second stacks of wafers to serve as electrical contacts between active IC devices on the first and second stacks of wafers.

Claim 33

Dependent Claim 61 words

29 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 27 , further comprising dummy vias arranged on opposing surfaces of the first and second stacks of adjacent wafers to increase the surface area for wafer-to-wafer bonding and serve as auxiliary structures such as ground planes or heat conduits for the active IC devices on vertically stacked wafers.

Claim 34

Dependent Claim 47 words

30 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 27 , wherein the vias are formed tapered from the top to the bottom via trench to increase the surface area for wafer to-wafer bonding in the first and second stacks of adjacent wafers.

Claim 35

Dependent Claim 122 words

31 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 27 , wherein each via is formed by a dual damascene process comprised of: selectively etching the top wafer to form an upper trench section of a via; depositing an oxide layer to insulate a sidewall of the upper trench section of the via; etching the oxide layer in the upper trench section of the via to form a lower trench section of the via; depositing a barrier/seed layer in the upper trench section and the lower trench section of the via; and depositing a conduction metal on the barrier/seed layer for providing an electrical connection between active IC devices on the vertically stacked wafers and the external interconnect.

Claim 36

Dependent Claim 101 words

32 . The three-dimensional (3-D) vertically stacked wafer system as claimed in claim 31 , wherein the barrier/seed layer includes a barrier layer comprised of a material selected from one of the group including tantalum (Ta), tantalum (TaN), titanium (Ti), and tungsten (W), and deposited in the upper trench section overlying the oxide layer and the lower trench section of the via; and a copper (Cu) seed layer comprised of a thin layer of copper (Cu) deposited on the barrier layer, and deposited overlying the barrier layer in both the upper trench section and the lower trench section of the via.

Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices

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