US20020001905A1
Expired / Lapsed
US
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Vertical nano-size transistor using carbon nanotubes and manufacturing method thereof
Assignee: Samsung Electronics Co Ltd
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Filing: 2001-06-27
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Granted: —
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Expires: 2021-06-27
Abstract
Abstract The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.
Inventors
- 👤 Won-bong Choi
- 👤 Jo-won Lee
- 👤 Young-Hee Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 05:18
CPC Classifications
G; G11; G11C; G11C13/00; G11C13/02; G11C13/025; H; H10; H10D; H10D10/00; H10D10/40; B; B82; B82Y; B82Y10/00; H10D30/00; H10D30/01; H10D30/014; H10D30/40; H10D30/43; H10K; H10K10/00; H10K10/40; H10K10/46; H10K85/00; H10K85/20; H10K85/221; G11C2213/00; G11C2213/10; G11C2213/17; H10K10/462; H10K10/491; Y; Y10; Y10S; Y10S977/00; Y10S977/70; Y10S977/701; Y10S977/708; Y10S977/723; Y10S977/734; Y10S977/742; Y10S977/84; Y10S977/842; Y10S977/843; Y10S977/902; Y10S977/932; Y10S977/936; Y10S977/938
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
72 words
1 . A vertical nano-sized transistor using carbon nanotubes comprising: an insulating layer having holes, the holes having nano-sized diameters; carbon nanotubes vertically aligned in the holes; gates formed over the insulating layer in the vicinity of the carbon nanotubes; a nonconductor film deposited on the gates to fill the holes; drains formed over the nonconductor film and the carbon nanotubes; and sources formed under the insulating layer and the carbon nanotubes.
Claim 2
Dependent Claim
72 words
1 . A vertical nano-sized transistor using carbon nanotubes comprising: an insulating layer having holes, the holes having nano-sized diameters; carbon nanotubes vertically aligned in the holes; gates formed over the insulating layer in the vicinity of the carbon nanotubes; a nonconductor film deposited on the gates to fill the holes; drains formed over the nonconductor film and the carbon nanotubes; and sources formed under the insulating layer and the carbon nanotubes.
Claim 3
Dependent Claim
35 words
2 . The vertical nano-sized transistor using carbon nanotubes according to claim 1 , wherein the insulating layer is formed of a material selected from the group consisting of Al 2 O 3 and Si.
Claim 4
Dependent Claim
25 words
3 . The vertical nano-sized transistor using carbon nanotubes according to claim 1 , wherein the sources and the drains are formed of metal films.
Claim 5
Dependent Claim
105 words
4 . A method of manufacturing a vertical nano-sized transistor using carbon nanotubes, comprising: (a) forming sources on a semiconductor substrate; (b) forming an insulating layer using a nonconductor material and forming holes having nano-sized diameters in the insulating layer at portions of the insulating layer corresponding to the sources, where the holes are spaced at intervals of several nanometers; (c) vertically growing carbon nanotubes on the sources in the holes; (d) forming gates in the vicinity of the carbon nanotubes; (e) depositing a nonconductor film over the gates to fill the holes; and (f) forming drains over the nonconductor film and the carbon nanotubes.
Claim 6
Dependent Claim
105 words
4 . A method of manufacturing a vertical nano-sized transistor using carbon nanotubes, comprising: (a) forming sources on a semiconductor substrate; (b) forming an insulating layer using a nonconductor material and forming holes having nano-sized diameters in the insulating layer at portions of the insulating layer corresponding to the sources, where the holes are spaced at intervals of several nanometers; (c) vertically growing carbon nanotubes on the sources in the holes; (d) forming gates in the vicinity of the carbon nanotubes; (e) depositing a nonconductor film over the gates to fill the holes; and (f) forming drains over the nonconductor film and the carbon nanotubes.
Claim 7
Dependent Claim
32 words
5 . The method according to claim 4 , wherein while forming the insulating layer, the nonconductor material is one selected from the group consisting of Al 2 O 3 and Si.
Claim 8
Dependent Claim
28 words
6 . The method according to claim 4 , wherein vertically growing carbon nanotubes is performed by one method selected from chemical vapor deposition, electrophoresis and mechanical compression.
Claim 9
Dependent Claim
61 words
7 . A vertical nano-sized transistor using carbon nanotubes comprising: an insulating layer having holes, the holes having nano-sized diameters; carbon nanotubes vertically aligned in the holes; drains formed over the insulating layer and the carbon nanotubes; a nonconductor film deposited on the drains; gates formed over the nonconductor film; and sources formed under the insulating layer and the carbon nanotubes.
Claim 10
Dependent Claim
61 words
7 . A vertical nano-sized transistor using carbon nanotubes comprising: an insulating layer having holes, the holes having nano-sized diameters; carbon nanotubes vertically aligned in the holes; drains formed over the insulating layer and the carbon nanotubes; a nonconductor film deposited on the drains; gates formed over the nonconductor film; and sources formed under the insulating layer and the carbon nanotubes.
Claim 11
Dependent Claim
35 words
8 . The vertical nano-sized transistor using carbon nanotubes according to claim 7 , wherein the insulating layer is formed of one material selected from the group consisting of Al 2 O 3 and Si.
Claim 12
Dependent Claim
25 words
9 . The vertical nano-sized transistor using carbon nanotubes according to claim 7 , wherein the sources and the drains are formed of metal films.
Claim 13
Dependent Claim
99 words
10 . A method of manufacturing a vertical nano-sized transistor using carbon nanotubes, comprising: (a) forming sources on a semiconductor substrate; (b) forming an insulating layer using a nonconductor material and forming holes having nano-sized diameters in the insulating layer at portions of the insulating layer corresponding to the sources, and the holes and being spaced at intervals of several nanometers; (c) vertically growing carbon nanotubes on the sources in the holes; (d) forming drains over the nonconductor film and the carbon nanotubes; (e) depositing a nonconductor film over the drains; and (f) forming gates over the nonconductor film.
Claim 14
Dependent Claim
99 words
10 . A method of manufacturing a vertical nano-sized transistor using carbon nanotubes, comprising: (a) forming sources on a semiconductor substrate; (b) forming an insulating layer using a nonconductor material and forming holes having nano-sized diameters in the insulating layer at portions of the insulating layer corresponding to the sources, and the holes and being spaced at intervals of several nanometers; (c) vertically growing carbon nanotubes on the sources in the holes; (d) forming drains over the nonconductor film and the carbon nanotubes; (e) depositing a nonconductor film over the drains; and (f) forming gates over the nonconductor film.
Claim 15
Dependent Claim
32 words
11 . The method according to claim 10 , wherein while forming the insulating layer, the nonconductor material is one selected from the group consisting of Al 2 O 3 and Si.
Claim 16
Dependent Claim
28 words
12 . The method according to claim 10 , wherein vertically growing carbon nanotubes is performed by one method selected from chemical vapor deposition, electrophoresis and mechanical compression.
References Cited (Backward Citations)
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