US12197374B2
Active / In Force
US
⏱️ 14.6 years remaining
Peer-to-peer link sharing for upstream communications from XPUS to a host processor
Assignee: Intel Corp
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Filing: 2021-06-25
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Granted: 2025-01-14
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Expires: 2041-06-25
Abstract
Abstract A processor unit comprising a first controller to couple to a host processing unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host central processing unit via a third link; and circuitry to determine whether to send a cache coherent request to the host central processing unit over the first link or over the second link via the second processing unit.
Inventors
- 👤 Rahul Pal
- 👤 Nayan Amrutlal Suthar
- 👤 David M. Puffer
- 👤 Ashok Jagannathan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:46
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; H; H04; H04W; H04W76/00; H04W76/20; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F13/40; G06F13/4004; G06F13/4022; G06F13/4282; G06F15/00; G06F15/16; G06F15/163; G06T; G06T1/00; G06T1/20; G06T1/60; H04W72/00; H04W72/04; H04W72/12; H04W72/1221; H04W76/10; H04W76/15; G06F12/0813; G06F2212/00; G06F2212/10; G06F2212/1016; G06F2212/1024; G06F2212/50; G06F2212/507; G06F2212/62; G06F2212/621; G06F2213/00; G06F2213/0026; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
79 words
A processor unit comprising: a first controller to couple to a host processor unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host processor unit via a third link; and circuitry to determine whether to send a cache coherent request to the host processor unit over the first link or over the second link via the second processor unit.
Claim 2
Dependent Claim
79 words
A processor unit comprising: a first controller to couple to a host processor unit over a first link; a second controller to couple to a second processor unit over a second link, wherein the second processor unit is to couple to the host processor unit via a third link; and circuitry to determine whether to send a cache coherent request to the host processor unit over the first link or over the second link via the second processor unit.
Claim 3
Dependent Claim
25 words
The processor unit of claim 1 , wherein the first link and the third link are each links according to a Compute Express Link protocol.
Claim 4
Dependent Claim
41 words
The processor unit of claim 1 , wherein the circuitry is to determine whether to send the cache coherent request over the first link or over the second link based on an amount of available upstream bandwidth over the first link.
Claim 5
Dependent Claim
31 words
The processor unit of claim 3 , wherein the circuitry is to determine the amount of available upstream bandwidth over the first link based on a number of link credits available.
Claim 6
Dependent Claim
30 words
The processor unit of claim 3 , wherein the circuitry is to determine the amount of available upstream bandwidth over the first link based on a raw upstream bandwidth metric.
Claim 7
Dependent Claim
40 words
The processor unit of claim 1 , wherein the circuitry is to determine whether to send the cache coherent request over the first link or over the second link based on an amount of available bandwidth over the second link.
Claim 8
Dependent Claim
41 words
The processor unit of claim 1 , wherein the circuitry is to determine whether to send the cache coherent request over the first link or over the second link based on an amount of available upstream bandwidth over the third link.
Claim 9
Dependent Claim
59 words
The processor unit of claim 7 , wherein the circuitry is to determine the amount of available upstream bandwidth over the third link based on a number of host-bound requests received by the processor unit from the second processor unit, wherein the processor unit is to send the host-bound requests to the host processor unit over the first link.
Claim 10
Dependent Claim
42 words
The processor unit of claim 1 , further comprising second circuitry to: track memory requests received from the second processor unit for memory of the host processor unit; and respond to snoop requests associated with such memory from the host processor unit.
Claim 11
Dependent Claim
21 words
The processor unit of claim 1 , wherein the processor unit and the second processor unit are each graphics processing units.
Claim 12
Independent Claim
78 words
A method comprising: communicating, by a first processor unit, with a host processor unit over a first link; communicating, by the first processor unit, with a second processor unit over a second link, wherein the second processor unit is to couple to the host processor unit via a third link; and determining whether to send a cache coherent request to the host processor unit over the first link or over the second link via the second processor unit.
Claim 13
Independent Claim
78 words
A method comprising: communicating, by a first processor unit, with a host processor unit over a first link; communicating, by the first processor unit, with a second processor unit over a second link, wherein the second processor unit is to couple to the host processor unit via a third link; and determining whether to send a cache coherent request to the host processor unit over the first link or over the second link via the second processor unit.
Claim 14
Dependent Claim
37 words
The method of claim 11 , further comprising determining whether to send the cache coherent request over the first link or over the second link based on an amount of available upstream bandwidth over the first link.
Claim 15
Dependent Claim
36 words
The method of claim 11 , further comprising determining whether to send the cache coherent request over the first link or over the second link based on an amount of available bandwidth over the second link.
Claim 16
Dependent Claim
37 words
The method of claim 11 , further comprising determining whether to send the cache coherent request over the first link or over the second link based on an amount of available upstream bandwidth over the third link.
Claim 17
Dependent Claim
38 words
The method of claim 11 , further comprising: tracking memory requests received from the second processor unit for memory of the host processor unit; and responding to snoop requests associated with such memory from the host processor unit.
Claim 18
Independent Claim
102 words
A system comprising: a host processor unit; and a plurality of processor units, a processor unit of the plurality of processor units coupled to the host processor unit via a first link and to other processor units of the plurality of processor units via a plurality of second links, the other processor units coupled to the host processor unit via a plurality of third links; wherein the processor unit is to determine whether to send a cache coherent request to the host processor unit over the first link or over one of the second links via one of the other processor units.
Claim 19
Independent Claim
102 words
A system comprising: a host processor unit; and a plurality of processor units, a processor unit of the plurality of processor units coupled to the host processor unit via a first link and to other processor units of the plurality of processor units via a plurality of second links, the other processor units coupled to the host processor unit via a plurality of third links; wherein the processor unit is to determine whether to send a cache coherent request to the host processor unit over the first link or over one of the second links via one of the other processor units.
Claim 20
Dependent Claim
43 words
The system of claim 16 , wherein the processor unit is to determine whether to send the cache coherent request over the first link or over one of the second links based on an amount of available upstream bandwidth over the first link.
Claim 21
Dependent Claim
43 words
The system of claim 16 , wherein the processor unit is to determine whether to send the cache coherent request over the first link or over one of the second links based on an amount of available upstream bandwidths over the second links.
Claim 22
Dependent Claim
33 words
The system of claim 16 , wherein the processor unit is to send a plurality of cache coherent requests to the host processor unit via a first plurality of the other processor units.
Claim 23
Dependent Claim
51 words
The system of claim 16 , wherein the processor unit is to: track memory requests received from a second processor unit of the plurality of processor units, the memory requests for memory of the host processor unit; and respond to snoop requests associated with such memory from the host processor unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2028-01-14 | 2028-07-15 | 2029-01-14 | $2000.00 | Pending Window |
| 7.5 Years (Year 8) | 2032-01-14 | 2032-07-15 | 2033-01-14 | $3760.00 | Pending Window |
| 11.5 Years (Year 12) | 2036-01-14 | 2036-07-15 | 2037-01-14 | $7700.00 | Pending Window |