NZ196276A
Expired / Lapsed
NZ
⏱️ 0.0 years remaining
Digital exchange:fast processor for control functions
Assignee: Plessey Overseas
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Filing: 1981-02-16
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Granted: —
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Expires: 2001-02-16
Abstract
Abstract A digital telephone exchange including a first and second processor in which the second processor contains algorithms selectable by the first processor for operation of functions within the exchange, and in which subscribers' apparatus is connectable to both processors via bus structures and in which signals are passed along the bus structures between connected subscribers under the command of both processors.
Inventors
- 👤 W G Harris
- 👤 S J Mason
Bibliographic Details
Application Number
—
Jurisdiction
NZ
Data Source
google_patents
Last Synchronized
2026-11-02 23:55
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407
Claims Analysis
Total Claims: 1
Claim 1
Independent Claim
411 words
196276 *3;- "±& -;WHAT VIE CLAIM IS:;1 . A digital telephone exchange including a central processing unit for controlling the switching functions of the exchange including a fast signal processor and 5 a time division multiplex network controller connected via a two way bus to the central processing unit, the fast signal processor performing the control functions for the exchange and including a time division multiplex highway comprising a data bus and a command bus connected 10 to the time division multiplex network controller and to the fast signal processor, the subscribers being connected to the time division multiplex highway, the arrangement being such that the central processing unit can access the fast signal processor and the subscribers via the 15 time division multiplex network controller and in which the subscribers can access the central processing unit via the time division multiplex network controller and the fast signal processor via the time division multiplex highway.;20 2. A digital telephone exchange as claimed in claim 1, in which the fast signal processor comprises a programme memory, a micro-processor, a scratchpad memory a data in first in first out store, a receive command first in first out store and a data out random access memory store 25 all connected to the micro-processor via an address bus f4f p8MARm^\;196276;25;and a data bus, in which a receive command decoder is connected to said receive command store and a transmit command decoder is connected to said data out random access memory store; said receive command decoder, said 5 transmit command decoder, said in first in first out store and said data out random access memory store being connected to the time division multiplex highway to which highway the subscribers lines and trunk lines and digital tie lines are connected, the command bus 10 and the data bus of the time division multiplex highway being connected such that the data bus is connected to the data in first in first out store and the data out random access memory store and the command bus is connected to the receive command decoder and the transmit 15 command decoder.;3. A digital telephone exchange as claimed in claim 2 in which other main central processor peripheral units are connected to the two way bus connecting said central processing unit and said fast signal processor. 20 4. A digital telephone exchange substantially as described with reference to the accompanying drawings.;PLESSEY OVERSEAS LIMITED By Their Attorneys HENRY HUGHES LIMITED Per:;f < Pt2*HARt984
References Cited (Backward Citations)
No citation records indexed.
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