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JPS6489537A Expired / Lapsed JP ⏱️ 0.0 years remaining

Lsi

Assignee: Toshiba Corp
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Filing: 1987-09-30
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Granted: —
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Expires: 2007-09-30
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Abstract

Abstract PURPOSE:To shorten wiring lengths by arranging both P-type semiconductor cells and N-type semiconductor cells so that each type of cell relatively neighbors in both row and column directions. CONSTITUTION:P-type semiconductor cells and N-type semiconductor cells are so arranged that each type of cell relatively neighbors in both row and column directions, or a pattern of P, N, P, N... in the row direction and a pattern of N, P, N, P... appear. According to the constitution, it is possible to make connections between the P-type semiconductor cell and the N-type semiconductor cell in both row and column directions, thereby allowing formation of a flip-flop, etc., in either direction, lengthwise or widthwise. Hence, when forming a flip-flop, etc., wiring lengths can be shortened, whereby a delay time can be reduced.

Inventors

  • 👤 Akiyasu Yamamoto

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 09:29
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907

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Total Claims: 0
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