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JPS6489445A Expired / Lapsed JP ⏱️ 0.0 years remaining

Wiring method of semiconductor integrated circuit device

Assignee: Toshiba Corp
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Filing: 1987-09-30
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Granted: —
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Expires: 2007-09-30
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Abstract

Abstract PURPOSE:To arrange input/output circuit blocks at desired positions, to reduce the size of a chip and to improve integration density, with respect to a wiring region between peripheral input/output circuit blocks and inner blocks, by dividing the region into four channels, providing restricting conditions for each channel, performing wiring, and overlapping the channel regions. CONSTITUTION:Each block has a rectangular shape, and the width, the height and the size of a chip are determined. The positions of four peripheral input/ output circuit blocks B5-B8 are fixed with the coordinates from an original point O of the chip. When the channels of the blocks are wired by a channel wiring method, there are restrictions caused by the model of the channel wiring in processing sequence. For example, when the channel CH1 is wired, the wiring of the channels CH2 and CH3 must be finished. It is necessary without fail that the four peripheral channels are processed after the channels in the inner blocks have been processed. In this way, the wiring is performed by effectively using the wiring region between the peripheral input/output circuit blocks and the inner blocks. Therefore, the integrating density of the semiconductor integrated chip can be improved.

Inventors

  • 👤 Mototaka Kuribayashi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 11:50
CPC Classifications
—

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