Semiconductor device

Abstract

Abstract PURPOSE: To reduce the area of a parasitic region and to achieve high performance and high density in a MOSFET, in a semiconductor device having a MIS structure, by providing a polycrystalline silicon layer, which is formed on a part from a source region to an element isolating region, providing the source region and a drain region, which are formed in a self-aligning mode, and providing a gate electrode, which is formed along an insulating film. CONSTITUTION: A channel region is determined with an N + type polycrystalline silicon layer 5 by a self-aligning mode. A gate electrode 8, which is selected from among a polycrystalline silicon layer, high melting point metal, metal and metal silicide, is formed on the channel region through a gate film 6. Source/drain regions 3 and 4 are formed in a self-aligning mode by the diffusion of impurities from the N + type polycrystalline silicon layer 5. Lead-out of the source/drain electrodes is performed with said N + type polycrystalline silicon layer 5. Therefore, the size of an element can be reduced without restriction on lithography technology. As a result, parasitic element such as a drain- substrate capacitance are decreased to a large extent. The high performance and the high density of the element can be achieved. COPYRIGHT: (C)1989,JPO&Japio

Inventors

• 👤 Tomoyuki Furuhata

Bibliographic Details