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JPS6473447A Expired / Lapsed JP ⏱️ 0.0 years remaining

System for controlling low order device

Assignee: Fujitsu Ltd
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Filing: 1987-09-16
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Granted: —
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Expires: 2007-09-16
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Abstract

Abstract PURPOSE:To speed up an interrupting processing without imposing a big burden on a low-order central processor by providing a signal line for transmitting an interrupting signal from a low-order device to the low-order central processor to a bus adapter part between the low-order device and the bus adapter part. CONSTITUTION:The signal line 7 for transmitting the interrupting signal transmitted from the low-order device 6 to the low-order central processor 5 to the bus adapter part 3 between the low-order device 6 and the bus adapter part 3. Consequently, the interrupting signal from the low-order device 6 is appropriately processed by the command of the high-order central processor 1 and the like according to whether the high-order central processor 1 or the low-order central processor 5 has instructed of starting even if the low-order central processor 5 does not judge the device which has instructed of starting. Thus, the interrupting processing can be executed without imposing the big burden on the low-order central processor 5.

Inventors

  • 👤 Shinji Ineshima
  • 👤 Masahisa Kageyama
  • 👤 Yasushi Oi
  • 👤 Shinichi Yokomizo
  • 👤 Junko Takeshita

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 19:33
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24

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