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JPS6466899A Expired / Lapsed JP ⏱️ 0.0 years remaining

Memory cell

Assignee: Ramtron International Corp
•
Filing: 1988-07-01
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Granted: —
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Expires: 2008-07-01
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Abstract

Abstract PURPOSE: To solve the polarization fatigue problem of a ferroelectric substance material and to obtain a high speed nonvolatile semiconductor memory by providing internal nodes and accumulating the conditions of the nodes to a memory cell at various time. CONSTITUTION: A memory cell 10 is provided with first and second parts. A first part 12 has a volatile memory and a second part 14 is provided with the circuit which includes the ferroelectric substance device that is connected to the part 12. The part 12 includes the flip-flop which consists of two n channel transistors 16 and 18 and two p channel transistors 20 and 22. A pair of nodes A and B is cross coupled to the gate electrodes of the transistors 16 to 22. A node C is connected to a zero volt VSS and a node D couples the source electrodes of the transistors 20 and 22 to a signal CLKI. The signal CLKI is normally at a VCC level. Thus, data writing and reading are conducted for the flip-flop, which consists of cross coupled transistors, by accessing to bit lines 28 and 30 and a word line.

Inventors

  • 👤 Klaus Dimmler
  • 👤 S Sheffield Eaton Jr

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 09:29
CPC Classifications
G; G11; G11C; G11C14/00; G11C14/0054; G11C14/0072; G11C11/00; G11C11/21; G11C11/22

Claims Analysis

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References Cited (Backward Citations)

JPS5723354A Cited

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