Memory access control system

Abstract

Abstract PURPOSE:To eliminate the idle time of banks and to improve the throughput, by performing the mutual interleaves in the bank idle time while monitoring the interleave distances among plural pipelines set in a main memory. CONSTITUTION:A priority order deciding means A receives the request signals from (m) pieces of memory control units MCU and gives the priority orders to (l) pieces of these units. An address latch means B receives the corresponding address signals and latches them. A way address distance monitor means C always monitors the distances among way addresses of the MCUs to perform the continuous accesses to (l) pieces of MCUs received the priority orders as well as to (n) ways. Then the means C supplies the start signals to (l) pieces of pipelines D when said distances are equal to P (p=n/l, p>=1). A timing signal generating means E produces the timing signals and (l) pieces of MCU perform the page accesses to a main memory MSU at one time.

Inventors

• 👤 Katsumi Miwata
• 👤 Isao Azuma

Bibliographic Details