Asynchronous signal synchronizing circuit

Abstract

Abstract PURPOSE:To considerably economize the amount of hardware even in case of the increase of the number of busses for control data by sharing registers for interface to the external between data transmission and reception. CONSTITUTION:When an asynchronous signal synchronizing and sending part 1 is operated in the reception mode, asynchronous reception data which is received from a device 2 through a transmission/reception part 3 is held in a data holding part 7 and is transmitted to a processor 5 synchronously with the internal clock outputted from a synchronous signal part 6. When the asynchronous signal synchronizing and sending part 1 is operated in the transmission mode, transmission data sent from the processor 5 is held in the data holding part 7 and is sent to the device 2 through the transmission/reception part 3. In this case, the data holding part 7 has registers having the same width as the bus width, and these registers are simultaneously controlled for synchronization by the clock of the synchronous signal part 6. Thus, it is sufficient if registers are extended in case of extension of the bus width.

Inventors

• 👤 Masabumi Morihara

Bibliographic Details