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JPS645074A Expired / Lapsed JP ⏱️ 0.0 years remaining

Field effect transistor

Assignee: Sharp Corp
•
Filing: 1987-06-26
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Granted: —
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Expires: 2007-06-26
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Abstract

Abstract PURPOSE:To obtain a large mutual conductance by a method wherein a semiconductor layer has a three-layer laminated structure composed of a 1st semiconductor layer which is not doped with a donor impurity, a 2nd semiconductor layer which is doped with a donor impurity and formed on the 1st semiconductor layer and a 3rd semiconductor layer which has a smaller electron affinity than the 2nd semiconductor layer and is not doped with a donor impurity and formed on the 2nd semiconductor layer. CONSTITUTION:A nondoped GaAs layer 1, an In0.2Ga0.8As layer 2 and a nondoped GaAs layer 3 are successively formed on a GaAs semi-insulating substrate 5. An atomic layer plane 4 which is doped with atoms of silicon as a donor impurity and in which channel electrons are produced is formed in the middle of the layer 2. A source electrode 6 and a drain electrode 7 are formed on the layer 3 and a gate electrode 8 is formed on the etched part of the layer 3. If the etched depth of the layer 3 is so selected as to make the distance between the electrode 8 and the layer plane 4 400Angstrom or less, the normally-ON type operation characteristics can be obtained and a mutual conductance as high as 400m /mm can be obtained.

Inventors

  • 👤 Tatsuya Yamashita
  • 👤 Masahiro Shioda

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 04:12
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS61276269A Cited

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