Data processor in rds receiver

Abstract

Abstract PURPOSE:To surely prevent the fetching of error data due to multipath disturbance by holding output data of a multipath detecting circuit for a time corresponding to one block and controlling error correction in an error correcting circuit based on this held data. CONSTITUTION:A multipath check routine is executed by the interruption at every timing of input data to a group and block synchronizing and error detecting circuit 12 from a decoder 9 with 26 bits as one group. When the detection output of a multipath detecting circuit 17 is generated, a multipath state counter is incremented. A processor temporarily stores the counted value of this counter in a register and reads out the counted value of the multipath state counter, which is obtained at the time of preceding processing, from the register. If the read counted value of the multipath state counter exceeds a prescribed value, the number of error correction bits is changed to control the error correction capability and data whose error is corrected by the new error correction capability is fetched.

Inventors

• 👤 Koichi Ryu
• 👤 Toshito Ichikawa
• 👤 Junichi Nishida

Bibliographic Details