Ecl level output circuit

Abstract

Abstract PURPOSE:To reduce the power consumption in a differential amplifier circuit by supplementing a base current of an output bipolar transistor(TR) via a FET. CONSTITUTION:A p-channel MOS field effect TR T1 is connected in parallel with a load resistor R1 in a bipolar differential amplifier circuit 3, a gate is connected to a connecting point between the TR Q1 and the load resistor R2 and the source is connected to a high potential power supply and an output VOS1 of the differential amplifier circuit 3 is connected to the drain. Since the current supplied to the base of the output drive circuit 4 is supplemented from the MOS TR T1 in this way, even when the current flowing to the loads R1, R2 is decreased, the output signal of the ECL level is obtained sufficiently and the current flowing to the loads R1, R2 is reduced. Thus, the power consumption is decreased.

Inventors

• 👤 Takakuni Douseki
• 👤 Yasuo Omori

Bibliographic Details