Semiconductor storage device

Abstract

Abstract PURPOSE:To shorten the stop time of a virtual storage type processor by outputting data stored in plural memory cells in a memory cell array which are coupled with a prescribed data line at all times without performing any selecting operation. CONSTITUTION:Indexes X1 and X2 of a logical address LA from a CPU are transmitted to a memory controller MMU to read an address translation buffer TLB associatively. Then the TLB is hit, a corresponding frame number FN is read out of the RAM of the TLB. When the TLB is mishit, on the other hand, the MU interrupts the processing of the CPU and a write address aw is determined based upon an address significance flag F outputted from the TLB to an address specifying circuit ASL at all times in parallel to paging processing by the translation table PTE of a main storage device MM. Consequently, the aw after the paging processing is selected instantaneously, the wait time is shortened, and the throughput is improved.

Inventors

• 👤 Hiroko Shinoki
• 👤 Makio Uchida

Bibliographic Details