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JPS6435934A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integrated circuit device

Assignee: Hitachi Microcomputer System Ltd
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Filing: 1987-07-30
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Granted: —
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Expires: 2007-07-30
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Abstract

Abstract PURPOSE:To contrive a reduction in the impedance of a power supply without increasing the size of a chip by a method wherein power wirings are provided on a memory cell array. CONSTITUTION:Power wirings 5a and 5b and wirings 6 for reinforcing word lines, which are extended to the direction parallel to the long sides of a semiconductor chip 1, are provided on a memory cell array M-ARY. These wirings 5a, 5b and 6 are all constituted of a second-layer Al film, for example. Using these power wirings, the power wiring of a semiconductor integrated circuit device can be reinforced without increasing the size of the chip. Accordingly, a reduction in the impedance of a power supply can be contrived without increasing the size of the chip.

Inventors

  • 👤 Shuichi Miyaoka
  • 👤 Nobuo Tanjiyou
  • 👤 Toshikazu Arai
  • 👤 Hiroshi Higuchi
  • 👤 Hisayuki Higuchi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 09:00
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/211; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W72/00; H10W72/90; Y; Y10; Y10S; Y10S257/00; Y10S257/915

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