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JPS6433799A Expired / Lapsed JP ⏱️ 0.0 years remaining

Sample holding circuit

Assignee: Sony Corp
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Filing: 1987-07-30
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Granted: —
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Expires: 2007-07-30
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Abstract

Abstract PURPOSE:To improve the distortion factor during a holding period by giving a prescribed potential through a voltage follower and a second switch to the connecting point of a first resistor and a first switch, which are directly connected between a signal input terminal and the non-inverse input terminal of an operational amplifier. CONSTITUTION:To a connecting point H of a first resistor 4 and a first switch 5, which are directly connected between a signal input terminal 3 and an on- inverse input plus terminal of an operational amplifier 1, a voltage follower 9 and a second switch 10 are connected. During the holding period, since the switch 5 is turned off and the switch 10 is turned on, a direct current voltage VDC is supplied from a power source terminal 7 through the voltage follower 9 and the switch 10 to the connecting point H. In such a time, currents (VDC-VOUT<2>)/(R1+R2) flow through a resistor 6 into an output terminal 8, and since these are direct currents,they do not influence the distortion factor. During the sample period, the switch 5 is turned on, the switch 10 is turned off, and since the connecting points H and H' are both VDCs and the same potential, an influence for a floating capacity does not occur, and an abnormal signal does not generated.

Inventors

  • 👤 Mitsuo Soneda
  • 👤 Yukiya Tanaka

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-08 06:17
CPC Classifications
—

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS6344300B2 Cited

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