Address error detecting system

Abstract

Abstract PURPOSE:To decrease the number of input/output signals of an LSI by using an address parity to give correction to the write and read data parities of a control memory inside the LSI so that no output of parity is required to an address line from the LSI. CONSTITUTION:A write data line is inverted by an inverting circuit 6 if an address parity line 104 is kept at '1' when data are written into a control memory 8. Then data are written into the memory 8 with an address line 103 defined as an address. In a data read mode a read data parity line 105 is inverted by an inverting circuit 7 as long as the line 104 is kept at '1'. Thus the data are inputted to a control memory reading register 4. The contents of the register 4 undergo the parity check via a parity checking circuit 5. Thus an error of the line 103 is checked by the circuit 5 so that no output of parity is required to the line 103 from an LSI 1. Therefore the number of input/output lines of the LSI 1 can be decreased.

Inventors

• 👤 Jun Kanatsu

Bibliographic Details