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JPS6431080A Expired / Lapsed JP ⏱️ 0.0 years remaining

Target-signal detecting circuit

Assignee: NEC Corp
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Filing: 1987-07-27
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Granted: —
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Expires: 2007-07-27
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Abstract

Abstract PURPOSE:To enhance the reliability of an apparatus and to facilitate the isolation of causes when a target signal is not detected, by operating discrete Fourier transformation (DFT) circuits in parallel for each range block. CONSTITUTION:Received signals are converted 3a and 3b into a real-part digital signal and an imaginary-part digital signal. The signals are stored in buffer memories 4a and 4b. DFT circuits 101--101-N receive the digital signals at the real part and the imaginary part corresponding to range blocks from the memories 4a and 4b. A required doppler filter group is formed in each range block. The result of the filtering in each doppler filter is sent into a target judging circuit 8. The circuits 101-1-101-N are operated in parallel. The DFT in the circuit 101-1-101-N are carried out for every unit range for data of 1 CPI data in series in the range block. Then the outputs of the N pieces of the circuit 101-1-101-N are received by the judging circuit 8. Thus, in which range block the target block is present is judged.

Inventors

  • 👤 Yoshio Hayashi

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 15:59
CPC Classifications
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Claims Analysis

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References Cited (Backward Citations)

JPS515918A Cited
JPS60165566A Cited

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