Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To increase the number of input/output pins by a method wherein an input/output buffer cell is constituted by a P-MOS for output use, an N-MOS for output use, a P-MOS for input and logic use and an N-MOS for input and logic use and these are arranged in a row in an arrangement direction. CONSTITUTION:An input/output buffer cell 5 is constituted by the following: a MOS transistor region 6 of a first conductivity type for output use; a MOS transistor region 7 of a second conductivity type for output use; a MOS transistor region 8 of the first conductivity type for input and logic use; a MOS transistor region 9 of the second conductivity type for input and logic use. These regions are arranged in a row in a direction running from a bonding pad 2 to an internal logic gate 3. By this setup, the size of the input/output buffer cell 5 in its arrangement direction is reduced; it is possible to install many bonding pads.

Inventors

• 👤 Takahiko Arakawa
• 👤 Kazuhiro Sakashita
• 👤 Satoru Kishida
• 👤 Toshiaki Hanibuchi
• 👤 Ichiro Tomioka

Bibliographic Details